1. Introduction
As the MOSFET gate length enters the nanoscale field, short channel effects such as threshold voltage roll-off and drain-induced-barrier-lowering become increasingly significant, which limit the scaling capability of MOSFET design[1, 2]. Downscaling MOSFETs to their limits is a key challenge faced by the nanoelectronic industry. Therefore, new designs and structures become necessary to overcome these challenges. Multi-gate design, particularly the double gate (DG) MOSFETs (Fig. 1), are very important in nanoscale CMOS circuit design. This is mainly due to the superior control of the short channel effects (SCEs) because of the reduced influence of the drain voltage on the channel charge. Accurate information extraction about the current-voltage (I-V) characteristics requires the solution of Schrödinger and Poisson equations based on the non-equilibrium Green's function (NEGF) formalism, assuming quantum effects are fully accounted[3]. However, from the nanoscale CMOS circuit design point of view even a 2D solution of numerical NEGF is an overkill approach in term of both terms: complexity and computational cost[3]. In this regard, therefore, a high computational speed is necessary if the model is to be implemented in circuit simulators (PSPICE, CADENCE,
In the present paper, we present an efficient and systematic technique for nanoscale DG MOSFETs modeling, where simple and accurate device models can be automatically achieved from a computational process to maximally reduce human trial and error efforts. The developed model should be able to correctly represent the I-V characteristics of the nanoscale device, and effectively capture the electrical behavior of the device due to process variations. In addition, the model should be formulated such that it can be conveniently incorporated into existing circuit simulators for high-level circuit simulation and yield design. Unlike the numerical models used to study the nanoscale structure, such as 2D numerical non-equilibrium Green's function (NEGF) formalism, which is complicated and requires a high computation time and storage memory, the proposed approach has a lower complexity and lower simulation time, which are the prerequisites of nanoelectronic circuit simulators.
2. Modeling methodology
Recently, artificial intelligence techniques (AI) have been recognized as an important approach in the semiconductor device computer-aided design area in addressing the growing challenges of designing the next generation of nanoelectronic devices, circuits, and systems[3, 9]. The AI-based methods represent important steps towards automating the device modeling process. However, because the genetic algorithms have to learn the device behavior from numerical or experimental databases without using existing device physical models like: drift-diffusion (D-D), hydrodynamic and gradual-channel approximation (HGCA), which makes the reliability of the AI-based model low and questionable. In GA, variables of a problem are represented as genes in a chromosome, and the chromosomes (population) are evaluated according to their fitness values. Given a random initial population GA operates in cycles called generations. The problem to be solved is defined in terms of an evaluation function (fitness function), which is used to evaluate the chromosomes. A chromosome evaluated as having a high fitness value is likely to be a good solution to the problem.
Implementation of GA requires the determination of six fundamental issues: chromosome representation, selection function, genetic operators, initialization, and evaluation function[14, 15].
One of the approaches for mapping between the accurate and approximate models is to correct the approximate model parameters so that the simulation results are based on an approximate model, and mimic the accurate simulation results. Based on the efficiency proven by NEGF for the modeling of nanoscale DG MOSFETs and the difficulty imposed at the moment by the constraints of the nanotechnology (sub-50 nm) to form an experimental database[3, 9], we have used the NEGF formalism as an accurate model.
The gradual channel approximation (GCA), which assumes that the quasi Fermi potential stays constant along the direction perpendicular to the channel, is used in our study as an approximated model. Accurate models for long channel double-gate MOSFETs[10, 16-18] have been recently developed using the conventional approach, showing good agreement with 2D numerical simulations. The inclusion of short-channel effects SCEs in undoped multiple gate MOS models, using physical equations and without decreasing the order of continuity of the devices, is still a modeling challenge. For devices with channel lengths shorter than 50 nm, the drift-diffusion mechanism may not be the dominant transport mechanism. Ballistic or quasiballistic transport may occur. Adequate models for nanoscale devices must consider the balllistic or quasi-ballistic regime[19, 20].
2.1 Drain current modeling
Breaking away from the premise of the GCA means that one needs to solve the Poisson equation given by
$ Δϕ(x,y)=qniεsie[ϕ(x,y)−ϕF]/Vth,
$
|
(1) |
where q is the electron charge,
$ ϕF(0,y)=0,
$
|
(2) |
$ ϕF(L,y)=Vds,
$
|
(3) |
$ ϕF(x)=VdsL2x2.
$
|
(4) |
The drain current of a symmetrical DG MOSFET assuming gradual channel approximation is given by
$ IDS=qμeff(x,y)n(x,y)dϕF(x)dx=qμeff(x,y)nie[ϕ(x,y)−ϕF]dϕF(x)dx,
$
|
(5) |
where
As shown, the parameters
According to Eqs. (1) and (5), in a semiconductor device, the basic variables are electron distribution (
$ f=1M∑Vds∑Vgs∑Tsi∑Tox∑L[ParNUM−ParGA−ANAParNUM]2,
$
|
(6) |
where f is the fitness value; Par
Taur in Ref. [22], has introduced a long channel model for the inversion charge of undoped DG MOSFET devices based on a 1D analytical solution of the Poisson equation incorporating only the mobile charge term as,
$ Qi=Cox[−2CoxV2thQ0+√(2CoxV2thQ0)2+4V2thln(1+eVgs−Vfb−ϕF+VT2Vth)],
$
|
(7) |
where
For silicon films thinner than 5 nm, quantum confinement should be considered; it leads to a reduction of the channel charge density and an increase of the threshold voltage.
From Eq. (7), we can see that an accurate model of the inversion charge depends mainly on the oxide capacitance and threshold voltage. Therefore, in order to develop an accurate charge model, new oxide capacitance and threshold voltage models, which include the quantum effects, should be introduced in Eq. (7).
Figure 3(a) shows the variation of the quantum oxide capacitance,
$ Coxq=Cox1+CoxYIεs,
$
|
(8) |
where
$ Coxq=Cox1+ξ1CoxTsi.
$
|
(9) |
Figure 3(b) shows the variation of the quantum threshold voltage,
$ VTq=VT+δVTq,
$
|
(10) |
with
$ δVTq=ξ2T2si,
$
|
(11) |
where
Now, substituting the quantum oxide capacitance,
$ Qiq=Coxq[−2CoxqV2thQ0+√(2CoxqV2thQ0)2+4V2thln(1+eVgs−Vfb−ϕF+VT+δVTq2Vth)].
$
|
(12) |
The fitting parameters (
The drain current for a DG MOSFET, including quantum effects, can be calculated from:
$ Idsq=μeffWL∫VdVsQiq(ϕF)dϕF,
$
|
(13) |
where W is the channel width. Using Eqs. (12) and (13) and after some mathematical manipulations, the variation of the channel voltage as a function of the inversion charge can be written as,
$ dϕF=−dQiq2dCoxq−Vth(dQiqQiq+dQiqQiq+2Q0).
$
|
(14) |
Writing
$ Idsq=μeffWL[Q2iqs−Q2iqdCoxq+4Vth(Qiqs−Qiqd)+VthQ0ln(Q0+2QiqdQ0+2Qiqs)].
$
|
(15) |
The charge densities at the source and the drain ends of the transistor
$ Qiqs=Qiq(x=0)=Qiq(ϕF=0),
$
|
(16) |
and
$ Qiqd=Qiq(x=L)=Qiq(ϕF=Vds).
$
|
(17) |
For a transistor with a very thick body, the low-field mobility,
$ μeff≈μ01+(EeffE0)δ=11+ηQiq2εsiE0,Eeff=Qiq2εsi,
$
|
(18) |
where
For an applied drain-source voltage, more than the saturation voltage (
$ ΔL=λlnϕd+√ϕ2d−ϕ2dsat+(λθvsatμeff)2ϕdsat+λθvsatμeff,
$
|
(19) |
where
$ Le=L−ΔL.
$
|
(20) |
In the drain current compact model (15), we replace channel length L by the effective channel length value (20) in order to include the channel length modulation effect.
3. Results and discussion
For the purpose of GA-based optimization of Eq. (12), routines and programs for GA computation were developed using MATLAB 7.2 and all simulations were carried out on a Pentium Ⅳ, 3 GHz, 1 GB RAM computer. For the implementation of the GA, tournament selection is employed which selects each parent by choosing individuals at random, and then choosing the best individual out of that set to be a parent. Scattered crossover creates a random binary vector. It then selects the genes where the vector is united from the first parent, and the genes where the vector is zero from the second parent, and combines the genes to form the child. In our case, the crossover rate and the mutation rate are equal to 0.8 and 0.2 respectively. An optimization process was performed for a population size of 20 and a maximum number of generations equal to 100, for which stabilization of the fitness function was obtained. The obtained results of the proposed approach are presented for the studied device in two-dimensional space. The transistor length is 20 nm with 20 mesh points and its thickness is 5 nm with 5 mesh points. Therefore, simulation data are 2D matrixes of 20 × 5. The quantum simulations, self-consistent computations, have been carried out using 2D Silvaco and nano-MOS2.5 numerical simulator tools[26, 27].
Figure 4 shows the inversion charge density versus the gate-source voltage for a nanoscale undoped DG MOSFET. The increase and the shift of the inversion charge density due to the QM effect are well predicted by our model, given in Eq. (12). For below threshold voltage and in the subthreshold regime, quantum and classical inversion charge densities are close to each other. However, for a high gate-source voltage, the electrons are strongly confined in the direction perpendicular to the Si-SiO2 interface due to the increasing influence of the vertical electric field component. Figure 4 presents the influence of film thickness on the electron concentration distribution, in which the quantum distribution of charge is obtained by coupling Schrödinger's equation to Poisson's equation. Note that the carrier profile is modified, where the most of the carriers flow in the middle of the film, not at the interfaces. In Fig. 5, an excellent fit was found between our inversion charge model and the numerical Poisson-Schrödinger self-consistent (NEGF) simulation.
Figure 6 presents comparisons between the target data (NEGF) and drain current data calculated by our model, Eq. (15), for both nanoscale DG MOSFET designs. We can see that the proposed model provides a good agreement for a very wide interval of geometrical and physical parameters for both the investigated nanoscale DG MOSFETs in comparison with numerical simulations. Hence, the proposed compact model can be used to predict other combinations of input variables (
The forgoing results show that our model makes it feasible to include quantum effects accurately and generally in a nanoelectronic device simulation. In order to show a comparison between the proposed model and other approaches in the field of nano-CMOS circuit simulation, Table 1 shows that the neural method (AI-based method) is a behavioral approach of modeling where the neural model is given as a black-box and defined by 3 different blocks: an input vector-weight matrix and activation function-output vector, in addition, the analytical model proposed by Hariharan et al.[8] is more complex, includes several fitting parameters, and does not take into account the very thin channel effects. Contrary, in our approach, the developed model is an accurate simple analytical closed expression that includes the channel length modulation, the very thin channel effects and 2 global optimized fitting parameters (
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4. Conclusion
In this paper, a new analytical model that includes quantum and channel length modulation effects for undoped nanoscale DG MOSFETs is presented. The 2D P-S self-consistent computation and gradual channel approaches are used as accurate and approximate models, respectively. In the proposed approach, the Genetic Algorithm technique is used for mapping parameters of the gradual channel model into a new space. With mapped parameters, the GCA model is capable of producing results for an accurate 2D numerical simulation. The presented analytical models for threshold voltage, threshold voltage shift, quantum oxide capacitance, inversion charge density and drain current overcome problems using classical models. The proposed models have several advantages such as accuracy, simplicity and applicability for a wide device dimension range. The proposed models can be extended to include hot carrier and degradation effects. However, new models and analytical expressions should be developed in this case. The encouraging obtained results have indicated that the proposed closed analytical form is particularly suitable for incorporatedion in electronic device simulators to study nanoscale CMOS circuits.