A high performance carrier stored trench bipolar transistor with a field-modified P-base region

Yue Qi; Zhigang Wang; Wanjun Chen; Bo Zhang

doi:10.1088/1674-4926/34/4/044008

J. Semicond. > 2013, Volume 34 > Issue 4 > 044008

SEMICONDUCTOR DEVICES

A high performance carrier stored trench bipolar transistor with a field-modified P-base region

Yue Qi¹, Zhigang Wang^1,, Wanjun Chen^{1, 2} and Bo Zhang^{1, 2}

+ Author Affiliations

Corresponding author: Wang Zhigang, Email:wangzhig_9728@qq.com

DOI: 10.1088/1674-4926/34/4/044008

Abstract: A novel high performance carrier stored trench bipolar transistor (CSTBT) with a field-modified P-base region is proposed. Due to the p-pillars inserted into the drift region extending the P-base region to the bottom of the trench gate, the electric field around the trench gate is modified, preventing the CSTBT from breakdown in advance caused by a concentration of the electric field at the edge of the trench gate. The p-pillars under the p-well forming the novel P-base region also provide extra paths for hole transportation. Thus, the switching time is also reduced. Simulation results have shown that the blocking voltage (BV) of the novel CSTBT is almost 430 V higher exhibiting avalanche breakdown properties compared with the conventional CSTBT. Moreover, the turn-off time of the novel structure is 0.3 μs (17%) shorter than the conventional CSTBT with the same gate length.

Key words: field-modified P-base region, high breakdown voltage, fast switching, CSTBT

References

[1]	Li Z, Qian M, Ma R, et al. Trench IGBT with carrier bypass region. ICCCAS, 2009:624
[2]	Sumitomo M, Asai J, Sakane H, et al. Low loss IGBT with partially narrow mesa structure (PNM-IGBT). ISPSD, 2012:17
[3]	Hu Hao, Chen Xingbi. A novel high speed lateral IGBT with a self-driven second gate. Journal of Semiconductors, 2012, 33(3):0340041 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=11081503&flag=1
[4]	Ye Jun, Fu Daping, Luo Bo, et al. A novel TFS-IGBT with a super junction floating layer. Journal of Semiconductors, 2010, 31(11):1140081 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=10052003&flag=1
[5]	Lu Shuojin, Wang Lixin, Lu Jiang, et al. Influence of electron irradiation on the switching speed in insulated gate bipolar transistors. Journal of Semiconductors, 2009, 30(6):0640081 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09010803&flag=1
[6]	Lutz J, Schlangenotto H, Scheuermann U, et al. Semiconductor power device. Heidelberg:Springer, 2011:327
[7]	Majumdar G. Recent and future IGBT evolution. PCC, 2007:355
[8]	Qian Mengliang, Li Zehong, Zhang Bo, et al. Insulated gate bipolar transistor with trench gate structure of accumulation channel. Journal of Semiconductors, 2010, 31(3):0340021 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09080204&flag=1
[9]	Takahashi H, Haruguchi H, Hagino H, et al. Carrier stored trench-gate bipolar transistor (CSTBT)——a novel power device for high voltage application. ISPSD, 1996:349
[10]	Kang X, Lu L, Santi E, et al. Characterization and modeling of the LPT CSTBT——the 5th generation IGBT. 38th IAS Annual Meeting, 2003:982
[11]	Takahashi T, Tomomatsu Y, Sato K. CSTBT(Ⅲ) as the next generation IGBT. ISPSD, 2008:72
[12]	Ma Rongyao, Li Zehong, Hong Xin, et al. Carrier scored trench-gate bipolar transistor with p-floating layer. Journal of Semiconductors, 2010, 31(2):0240041 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09082201&flag=1
[13]	Zhang Jinping, Li Zehong, Zhang Bo, et al. A novel high voltage light punch-through carrier stored trench bipolar transistor with buried p-layer. Chin Phys B, 2012, 21:0685041
[14]	Adler M S, Temple V A K, Ferro A P, et al. Theory and breakdown voltage for planar devices with a single field limiting ring. IEEE Trans Electron Devices, 1977, 24(2):107 doi: 10.1109/T-ED.1977.18688
[15]	Cheng X, Sin J K O, Shen J, et al. A general design methodology for the optimal multiple-field-limiting-ring structure using device simulator. IEEE Trans Electron Devices, 2003, 50(11):2273 doi: 10.1109/TED.2003.815132
[16]	He Jin, Zhang Xin, Huang Ru, et al. A new quasi 2-dimensional analytical approach to predicting ring junction voltage, edge peak fields and optimal spacing of planar junction with single floating field limiting ring structure. Journal of Semiconductors, 2001, 22:700
[17]	Nakagawa A. Theoretical investigation of silicon limit characteristics of IGBT. ISPSD, 2006:5

Fig. 1. Schematic cross sections of the IGBT structures. (a) FMP-CSTBT. (b) CSTBT. (c) TIGBT

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Fig. 2. Feasible process for FMP-CSTBT. (a) P$^{+}$ implantation and drive in forming the CS body layer. (b) P$^{+}$ implantation and drive to fabricate the initial CS layer together with the CS body layer. (c) Dig grooves for p-pillars. (d) P-type silicon epitaxy and surface polish to form the p-pillars. (e) N-type silicon epitaxy with the same concentration of the N-substrate. (f) The rest of the process is compatible with trench IGBT

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Fig. 3. Electric field distribution of the IGBTs under the y location equals $L_{\rm g}$

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Fig. 4. Flowlines of IGBTs in the blocking state. (a) FMP-CSTBT ($L_{\rm g}$ = 5 μm, $L_{\rm CS}$ = 1 μm, $L_{\rm S-CS}$ = 0.5 μm, $W_{\rm CS}$ = 6 μm, $N_{\rm CS}$ = 5 × 10$^{15}$ cm$^{-3}$, $L_{\rm P}$ = 2 μm, $W_{\rm P}$ = 1 μm, $W_{\rm d}$ = 1 μm, $N_{\rm P}$ = 1 × 10$^{17}$ cm$^{-3}$, BV = 1480 V). (b) CSTBT1 ($L_{\rm g}$ = 4 μm, $L_{\rm CS}$ = 1 μm, $W_{\rm CS}$ = 7 μm, $N_{\rm CS}$ = 5 × 10$^{15}$ cm$^{-3}$, BV = 1310 V). (c) CSTBT2 ($L_{\rm g}$ = 5 μm, $L_{\rm CS}$ = 2 μm, $W_{\rm CS}$ = 7 μm, $N_{\rm CS}$ = 5 × 10$^{15}$ cm$^{-3}$, BV = 1050 V). (d) TIGBT ($L_{\rm g}$ = 4 μm, BV = 1420 V)

DownLoad: Full-Size Img PowerPoint

Fig. 5. Potential lines of IGBTs in the blocking state. (a) FMP-CSTBT ($L_{\rm g}$ = 5 μm, $L_{\rm CS}$ = 1 μm, $L_{\rm S-CS}$ = 0.5 μm, $W_{\rm CS}$ = 6 μm, $N_{\rm CS}$ = 5 × 10$^{15}$ cm$^{-3}$, $L_{\rm P}$ = 2 μm, $W_{\rm P}$ = 1 μm, $W_{\rm d}$ = 1 μm, $N_{\rm P}$ = 1 × 10$^{17}$ cm$^{-3}$, BV = 1480 V). (b) CSTBT1 ($L_{\rm g}$ = 4 μm, $L_{\rm CS}$ = 1 μm, $W_{\rm CS}$ = 7 μm, $N_{\rm CS}$ = 5 × 10$^{15}$ cm$^{-3}$, BV = 1310 V). (c) CSTBT2 ($L_{\rm g}$ = 5 μm, $L_{\rm CS}$ = 2 μm, $W_{\rm CS}$ = 7 μm, $N_{\rm CS}$ = 5 × 10$^{15}$ cm$^{-3}$, BV = 1050 V). (d) TIGBT (($L_{\rm g}$ = 4 μm, BV = 1420 V)

DownLoad: Full-Size Img PowerPoint

Fig. 6. The blocking characteristics of IGBTs

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Fig. 7. Hole current distribution in the forward conduction state of FMP-CSTBT

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Fig. 8. I-V characteristics in the forward conduction state of IGBTs

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Fig. 9. The relationship between the specific on-resistance and the breakdown voltage

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Fig. 10. Comparison of the turn-off time between FMP-CSTBT and CSTBTs

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Fig. 11. Minority carrier distributions in the turn-off process

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Table 1. Design parameters used for IGBTs

[1]	Li Z, Qian M, Ma R, et al. Trench IGBT with carrier bypass region. ICCCAS, 2009:624
[2]	Sumitomo M, Asai J, Sakane H, et al. Low loss IGBT with partially narrow mesa structure (PNM-IGBT). ISPSD, 2012:17
[3]	Hu Hao, Chen Xingbi. A novel high speed lateral IGBT with a self-driven second gate. Journal of Semiconductors, 2012, 33(3):0340041 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=11081503&flag=1
[4]	Ye Jun, Fu Daping, Luo Bo, et al. A novel TFS-IGBT with a super junction floating layer. Journal of Semiconductors, 2010, 31(11):1140081 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=10052003&flag=1
[5]	Lu Shuojin, Wang Lixin, Lu Jiang, et al. Influence of electron irradiation on the switching speed in insulated gate bipolar transistors. Journal of Semiconductors, 2009, 30(6):0640081 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09010803&flag=1
[6]	Lutz J, Schlangenotto H, Scheuermann U, et al. Semiconductor power device. Heidelberg:Springer, 2011:327
[7]	Majumdar G. Recent and future IGBT evolution. PCC, 2007:355
[8]	Qian Mengliang, Li Zehong, Zhang Bo, et al. Insulated gate bipolar transistor with trench gate structure of accumulation channel. Journal of Semiconductors, 2010, 31(3):0340021 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09080204&flag=1
[9]	Takahashi H, Haruguchi H, Hagino H, et al. Carrier stored trench-gate bipolar transistor (CSTBT)——a novel power device for high voltage application. ISPSD, 1996:349
[10]	Kang X, Lu L, Santi E, et al. Characterization and modeling of the LPT CSTBT——the 5th generation IGBT. 38th IAS Annual Meeting, 2003:982
[11]	Takahashi T, Tomomatsu Y, Sato K. CSTBT(Ⅲ) as the next generation IGBT. ISPSD, 2008:72
[12]	Ma Rongyao, Li Zehong, Hong Xin, et al. Carrier scored trench-gate bipolar transistor with p-floating layer. Journal of Semiconductors, 2010, 31(2):0240041 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09082201&flag=1
[13]	Zhang Jinping, Li Zehong, Zhang Bo, et al. A novel high voltage light punch-through carrier stored trench bipolar transistor with buried p-layer. Chin Phys B, 2012, 21:0685041
[14]	Adler M S, Temple V A K, Ferro A P, et al. Theory and breakdown voltage for planar devices with a single field limiting ring. IEEE Trans Electron Devices, 1977, 24(2):107 doi: 10.1109/T-ED.1977.18688
[15]	Cheng X, Sin J K O, Shen J, et al. A general design methodology for the optimal multiple-field-limiting-ring structure using device simulator. IEEE Trans Electron Devices, 2003, 50(11):2273 doi: 10.1109/TED.2003.815132
[16]	He Jin, Zhang Xin, Huang Ru, et al. A new quasi 2-dimensional analytical approach to predicting ring junction voltage, edge peak fields and optimal spacing of planar junction with single floating field limiting ring structure. Journal of Semiconductors, 2001, 22:700
[17]	Nakagawa A. Theoretical investigation of silicon limit characteristics of IGBT. ISPSD, 2006:5

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Received: 21 August 2012 Revised: 20 October 2012 Online: Published: 01 April 2013

Article Navigation > Journal of Semiconductors > 2013 > 34(4): 044008

Yue Qi, Zhigang Wang, Wanjun Chen, Bo Zhang. A high performance carrier stored trench bipolar transistor with a field-modified P-base region[J]. Journal of Semiconductors, 2013, 34(4): 044008. doi: 10.1088/1674-4926/34/4/044008 ****Y Qi, Z G Wang, W J Chen, B Zhang. A high performance carrier stored trench bipolar transistor with a field-modified P-base region[J]. J. Semicond., 2013, 34(4): 044008. doi: 10.1088/1674-4926/34/4/044008.

Citation:

Yue Qi, Zhigang Wang, Wanjun Chen, Bo Zhang. A high performance carrier stored trench bipolar transistor with a field-modified P-base region[J]. Journal of Semiconductors, 2013, 34(4): 044008. doi: 10.1088/1674-4926/34/4/044008 ****

Y Qi, Z G Wang, W J Chen, B Zhang. A high performance carrier stored trench bipolar transistor with a field-modified P-base region[J]. J. Semicond., 2013, 34(4): 044008. doi: 10.1088/1674-4926/34/4/044008.

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A high performance carrier stored trench bipolar transistor with a field-modified P-base region

DOI: 10.1088/1674-4926/34/4/044008

1.
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
2.
Institute of Electric and Information Engineering in Dongguan, University of Electronic Science and Technology of China, Dongguan 523808, China

Funds:

Project supported by the State Key Project of Science and Technology, China (No. 2011ZX02706-003)

the State Key Project of Science and Technology, China 2011ZX02706-003

More Information

Corresponding author: Wang Zhigang, Email:wangzhig_9728@qq.com
Received Date: 2012-08-21
Revised Date: 2012-10-20
Published Date: 2013-04-01

Abstract

Abstract

A novel high performance carrier stored trench bipolar transistor (CSTBT) with a field-modified P-base region is proposed. Due to the p-pillars inserted into the drift region extending the P-base region to the bottom of the trench gate, the electric field around the trench gate is modified, preventing the CSTBT from breakdown in advance caused by a concentration of the electric field at the edge of the trench gate. The p-pillars under the p-well forming the novel P-base region also provide extra paths for hole transportation. Thus, the switching time is also reduced. Simulation results have shown that the blocking voltage (BV) of the novel CSTBT is almost 430 V higher exhibiting avalanche breakdown properties compared with the conventional CSTBT. Moreover, the turn-off time of the novel structure is 0.3 μs (17%) shorter than the conventional CSTBT with the same gate length.
- field-modified P-base region,
- high breakdown voltage,
- fast switching,
- CSTBT

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References(17)

References

[1]	Li Z, Qian M, Ma R, et al. Trench IGBT with carrier bypass region. ICCCAS, 2009:624
[2]	Sumitomo M, Asai J, Sakane H, et al. Low loss IGBT with partially narrow mesa structure (PNM-IGBT). ISPSD, 2012:17
[3]	Hu Hao, Chen Xingbi. A novel high speed lateral IGBT with a self-driven second gate. Journal of Semiconductors, 2012, 33(3):0340041 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=11081503&flag=1
[4]	Ye Jun, Fu Daping, Luo Bo, et al. A novel TFS-IGBT with a super junction floating layer. Journal of Semiconductors, 2010, 31(11):1140081 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=10052003&flag=1
[5]	Lu Shuojin, Wang Lixin, Lu Jiang, et al. Influence of electron irradiation on the switching speed in insulated gate bipolar transistors. Journal of Semiconductors, 2009, 30(6):0640081 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09010803&flag=1
[6]	Lutz J, Schlangenotto H, Scheuermann U, et al. Semiconductor power device. Heidelberg:Springer, 2011:327
[7]	Majumdar G. Recent and future IGBT evolution. PCC, 2007:355
[8]	Qian Mengliang, Li Zehong, Zhang Bo, et al. Insulated gate bipolar transistor with trench gate structure of accumulation channel. Journal of Semiconductors, 2010, 31(3):0340021 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09080204&flag=1
[9]	Takahashi H, Haruguchi H, Hagino H, et al. Carrier stored trench-gate bipolar transistor (CSTBT)——a novel power device for high voltage application. ISPSD, 1996:349
[10]	Kang X, Lu L, Santi E, et al. Characterization and modeling of the LPT CSTBT——the 5th generation IGBT. 38th IAS Annual Meeting, 2003:982
[11]	Takahashi T, Tomomatsu Y, Sato K. CSTBT(Ⅲ) as the next generation IGBT. ISPSD, 2008:72
[12]	Ma Rongyao, Li Zehong, Hong Xin, et al. Carrier scored trench-gate bipolar transistor with p-floating layer. Journal of Semiconductors, 2010, 31(2):0240041 http://www.jos.ac.cn/bdtxben/ch/reader/view_abstract.aspx?file_no=09082201&flag=1
[13]	Zhang Jinping, Li Zehong, Zhang Bo, et al. A novel high voltage light punch-through carrier stored trench bipolar transistor with buried p-layer. Chin Phys B, 2012, 21:0685041
[14]	Adler M S, Temple V A K, Ferro A P, et al. Theory and breakdown voltage for planar devices with a single field limiting ring. IEEE Trans Electron Devices, 1977, 24(2):107 doi: 10.1109/T-ED.1977.18688
[15]	Cheng X, Sin J K O, Shen J, et al. A general design methodology for the optimal multiple-field-limiting-ring structure using device simulator. IEEE Trans Electron Devices, 2003, 50(11):2273 doi: 10.1109/TED.2003.815132
[16]	He Jin, Zhang Xin, Huang Ru, et al. A new quasi 2-dimensional analytical approach to predicting ring junction voltage, edge peak fields and optimal spacing of planar junction with single floating field limiting ring structure. Journal of Semiconductors, 2001, 22:700
[17]	Nakagawa A. Theoretical investigation of silicon limit characteristics of IGBT. ISPSD, 2006:5

A high performance carrier stored trench bipolar transistor with a field-modified P-base region

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