1. Introduction

The intelligent power module (IPM) is nowadays widely used as the power inverter circuit for appliance motor drive systems such as frequency-alterable air-conditioners, washing machines, and refrigerators. It is an advanced hybrid integrated circuit (IC) which contains power devices, driver IC and protection circuits. Due to their excellent performance, insulated gate bipolar transistors (IGBTs) are commonly employed as the power switching devices of the IPM, where they are required to switch on and off at high frequencies in order to reduce switching dissipation and improve system performance^[1]. However, this fast switching transient can lead to problems^[2-5]. One of the main issues caused by this switching transient that should be considered to properly design the IPM is the d$V$/d$t$ problem^{[3, 5-11]}. In the three-phase full-bridge IGBT inverter stage of the IPM, during the turn on transient of the high-side IGBT, there will be an abrupt voltage slope (d$V$/d$t$) applied across the collect-emitter terminals of the low-side IGBT. This d$V$/d$t$ can cause a current that flows into the gate drive circuit through the parasitic capacitances of the low-side IGBT, which leads to the increase of the gate-emitter voltage^{[9, 11]}. Even worse, if this unwanted voltage spike exceeds the threshold voltage of the low-side IGBT, an arm shoot through will occur, which threatens the reliability of the IGBT and IPM.

In order to improve d$V$/d$t$ immunity, increase the reliability of both the IGBT and IPM itself, it is therefore necessary to explore the theory behind the d$V$/d$t$ induced problem.

In this paper, an IGBT-based IPM which is used in a frequency-alterable air-conditioner system is proposed as the research subject and the d$V$/d$t$ effect on the IGBT gate circuit with respect to the real application circuit is investigated. Moreover, discussions are conducted for the analyzed results, working principle and causes of the problem, which provide a design reference to improve the reliability of the IGBT and IPM.

2. Circuit schematic and principal analysis

Figure 1 illustrates the simplified circuit schematic of the three-phase full-bridge inverter of the IPM and the corresponding photograph of the IPM is shown in Fig. 2. The inverter employs IGBT1-IGBT6 as the power switching devices which are arranged in three legs: U (IGBT1, IGBT4), V (IGBT3, IGBT6), W (IGBT5, IGBT2), each with its own anti-parallel free-wheeling diode (FWD) FWD1-FWD6.

In order to analyze the d$V$/d$t$ performance, a relevant circuit is shown in Fig. 3. In this Figure, the d$V$/d$t$ generated circuit is formed by $V_{1}$, $V_{2}$, $R_{1}$, $R_{2}$ and M2. Also, a PSpice model for IGBT is introduced. Since the IGBT is essentially a power MOSFET with an added semiconductor layer in series with the collector, it is suitable to emulate the basic function of the IGBT by a power MOSFET M1 in series with a PNP transistor Q1 connected as in Fig. 3. The collector-emitter diode, collector-emitter capacitance and breakdown features of the IGBT are emulated by D1 and D2. $R_{\rm C}$ and $R_{\rm E}$ indicate the collector and emitter resistances of the IGBT respectively. $C_{\rm GC}$ and $C_{\rm GE}$ are the parasitic gate-collector capacitance and gate-emitter capacitance of the IGBT respectively. $R_{\rm G}$ is the gate resistance and $R_{\rm DS(on)}$ indicates the resistance of the driver IC. In addition, stray inductance in the circuit from PCB tracks and die bonding wires of the IGBT are lumped together and represented by $L_{\rm S}$.

Referring to the circuit shown in Fig. 3, when the M2 turns on, there will be a sudden voltage slope (i.e. d$V$/d$t$) applied across the collector-emitter terminals of the IGBT. In this case, the d$V$/d$t$ can coupling into the gate circuit induces a current that flows in $C_{\rm GC}$, $R_{\rm G}$, $L_{\rm S}$ and $R_{\rm DS(on)}$ as shown in Fig. 3, and leads to a transitory voltage spike across the gate-emitter terminals of the IGBT. The voltage spike between the gate-emitter terminals of the IGBT is related to many parameters such as the applied d$V$/d$t$ across the collector-emitter terminals, the parasitic capacitances of the IGBT and the impedance of the gate drive circuit. This voltage spike can cause an increase of power dissipation. Moreover, if this voltage spike exceeds the threshold voltage of the IGBT, the device may self turn on, then the high-side IGBT and low-side IGBT will conduct simultaneously, resulting in an arm short through and threaten the reliability of the IGBT and IPM^[9].

From the equivalent circuit shown in Fig. 3, the circuit equations are given as follows:

$\begin{equation} \label{eq1} C_{\rm GC} \frac{{\rm d}V_{\rm CE}} {{\rm d}t}-C_{\rm GC} \frac{{\rm d}V_{\rm GE} }{{\rm d}t}-C_{\rm GE} \frac{{\rm d}V_{\rm GE} }{{\rm d}t}-i_{\rm G}=0, \end{equation}$

(1)

$\begin{equation} \label{eq2} V_{\rm GE} -i_{\rm G} R_{\rm G} -L_{\rm S} \frac{{\rm d}i_{\rm G}}{{\rm d}t}-i_{\rm G} R_{\rm DS(on)} =0, \end{equation}$

(2)

where $i_{\rm G}$ is the gate current of the IGBT. So, the gate-emitter voltage $V_{\rm GE}$ of the IGBT can be deduced from the above expressions and is given as follows:

$\begin{equation} \begin{split} \label{eq3} {}& \frac{V_{\rm GE} }{V_{\rm CE} } = \\& \frac{s (R_{\rm G} +R_{\rm DS(on)}) C_{\rm GC}} {1-\exp\left(-\dfrac{R_{\rm G} +R_{\rm DS(on)}} {L_{\rm S}}\right) +s (R_{\rm G} +R_{\rm DS(on)}) (C_{\rm GC} +C_{\rm GE})}. \end{split} \end{equation}$

(3)

When the value of the parasitic inductance $L_{\rm S}$ is very small compared with that of the gate resistance $R_{\rm G}+R_{\rm DS(on)}$, the $V_{\rm GE}$ can then be simplified by:

$\begin{equation} \begin{split} \label{eq4} V_{\rm GE} ={}&(R_{\rm G} +R_{\rm DS(on)}) C_{\rm GC} \frac{{\rm d}V_{\rm CE}}{{\rm d}t} \\[2mm]& \times \left\{1-\exp\left[\frac{t}{(R_{\rm G} +R_{\rm DS(on)}) (C_{\rm GC} +C_{\rm GE})}\right]\right\}. \end{split} \end{equation}$

(4)

In the above equation, it can be noted that the $V_{\rm GE}$ is directly affected by d$V_{\rm CE}$/d$t$, $C_{\rm GC}$ and $R_{\rm G}$, which could also be seen in Figs. 4-6. If the gate driver resistance $R_{\rm G}$ of the IGBT is too high, then during the d$V_{\rm CE}$/d$t$ transient, there will be a high voltage spike between the gate-emitter terminals of the IGBT and it is getting worse by the fact that the d$V_{\rm CE}$/d$t$ is changing fast or $C_{\rm GC}$ is high. So, the value of these parameters should be chosen carefully.

In the case that the value of $R_{\rm G}$ is very low, then a resonant circuit will be formed by $R_{\rm G}$, $R_{\rm DS(on)}$, $L_{\rm S}$, $C_{\rm GC}$ and $C_{\rm GE}$, which causes a voltage oscillation of the gate drive circuit as could be seen in Fig. 6.

A numerical simulation has been carried out with PSpice software to qualitatively analyze the d$V$/d$t$ effect. Several primary factors d$V$/d$t$, $C_{\rm GC}$ and $R_{\rm G}$ that influence the gate voltage spike were analyzed and the simulation results are shown in Figs. 4-6.

The d$V$/d$t$ induced gate voltage spikes for different d$V$/d$t$ rates were simulated when $R_{\rm G}$ $=$ 100 $\Omega$, $L_{\rm S}$ $=$ 100 nH, $R_{\rm DS(on)}$ $=$ 1 m$\Omega$, $C_{\rm GC}$ $=$ 10 pF and $C_{\rm GE}$ $=$ 700 pF. The simulation results are illustrated in Fig. 4. Obviously, the d$V$/d$t$ itself has a direct impact on the voltage spike. If a rapid d$V$/d$t$ is applied across the collector-emitter terminals of the IGBT, since the higher d$V$/d$t$ rate always generates a larger displace current, there is a quick rise rate of the voltage spike. It can be seen from Fig. 4 that the gate voltage spike is proportional to the d$V$/d$t$ rate. A lower d$V$/d$t$ rate leads to a lower voltage spike. When the collector-emitter voltage variation rate d$V$/d$t$ of the IGBT is 200 V/$\mu$s, there is a high voltage overshoot of about 2.25 V between the gate-emitter terminals of the IGBT, but the voltage spike duration time is very short, about 0.2 $\mu$s. When d$V$/d$t$ $=$ 50 V/$\mu$s, the voltage spike decreases to appropriately 1.15 V and the duration time becomes 0.4 $\mu$s. When d$V$/d$t$ $=$ 20V/$\mu$s, there is a significant reduction of the voltage spike, which is about 0.5V and the duration time increases to about 0.6 $\mu$s. Therefore, slowing down the d$V$/d$t$ rate can reduce the gate voltage spike, but on the other hand, the duration time of the voltage spike will increase accordingly.

Figure 5 shows the impact of the parasitic capacitances $C_{\rm GC}$ on the voltage spike when d$V$/d$t$ $=$ 200 V/$\mu$s, $R_{\rm G}$ $=$ 100 $\Omega$, $C_{\rm GE}$ $=$ 700 pF, $L_{\rm S}$ $=$ 100 nH and $R_{\rm DS(on)}$ $=$ 1 m$\Omega$. It is shown that by reducing $C_{\rm GC}$ from 160 to 10 pF, the gate voltage spike can be reduced by as much as 30%.

In Fig. 6, the simulated results for the d$V$/d$t$ induced gate voltage spikes at different gate resistances $R_{\rm G}$ are displayed when d$V$/d$t$ $=$ 200V/$\mu$s, $C_{\rm GC}$ $=$ 10 pF, $C_{\rm GE}$ $=$ 700 pF, $L_{\rm S}$ $=$ 100 nH and $R_{\rm DS(on)}$ $=$ 1m$\Omega$. It is shown that this parameter has a significant influence on the behavior of d$V$/d$t$. When the gate resistance $R_{\rm G}$ $=$ 100 $\Omega$, there is an obvious voltage spike between gate-emitter terminals of the IGBT during the d$V$/d$t$ transient, with a gate resistance of only 3 $\Omega$, the gate-emitter voltage spike is significantly reduced to about 0.5V. However, the large reduction in $R_{\rm G}$ can produce a ringing in the circuit. As has been mentioned before, this is due to the resonance of the gate circuit resistances, parasitic capacitances and stray inductances. Hence, $R_{\rm G}$ is the key factor for achieving optimized design, it is possible to control the d$V$/d$t$ induced voltage spike by choosing an appropriate value of gate resistance $R_{\rm G}$.

3. Experimental results

According to the previous theoretical analysis and simulation results of the d$V$/d$t$ effect on the IGBT gate circuit, an experimental study has been developed to inspect the performance of the d$V$/d$t$. Several IGBT devices were investigated and the parameters of the tested IGBTs are shown in Table 1. The d$V$/d$t$ induced gate voltage spikes were tested when d$V$/d$t$ $=$ 200 V/$\mu$s, 50 V/$\mu$s, 20 V/$\mu$s, $R_{\rm G}$ $=$ 100 $\Omega$, 20 $\Omega$, 3 $\Omega$ and $L_{\rm S}$ $=$ 100 nH, $R_{\rm DS(on)}$ $=$ 1 m$\Omega$ for devices A, B and C, respectively. The experimental results are given in Figs. 7-12. Device A and B are non-punch through (NPT) trench IGBTs and device C is a punch through (PT) planar IGBT. $V_{\rm th}$ is the threshold voltage of the IGBT.

It can be seen that the experimental results are similar to the simulation results shown in the above section. As could be seen from Figs. 7, 9 and 11, the d$V$/d$t$ rate has a direct influence on the voltage spike. A higher d$V$/d$t$ rate leads to a higher voltage spike but a lower duration time. Taking device A as an example, Figure 7 illustrates the tested waveforms according to changes in the d$V$/d$t$ rate. The amplitude of the voltage spike is approximately 1.85 V when d$V$/d$t$ is 200 V/$\mu$s, and it could be very much reduced as the d$V$/d$t$ rate reduces to 20 V/$\mu$s. Meanwhile, the duration time of the voltage spike also increased accordingly. Also, device A features the highest voltage spike compared to the other two devices B and C under the same conditions and the voltage spike of device C is lowest. This is because the voltage spike is proportional to the $C_{\rm GC}$ and inversely proportional to the $C_{\rm GE}$ as is shown in the simulation results.

The voltage spikes as a function of $R_{\rm G}$ for devices A, B and C are plotted in Figs. 8, 10 and 12. As seen from these figures, the experimental results agree with the simulation results that both the voltage spike and duration time are proportional to the $R_{\rm G}$. The higher the $R_{\rm G}$ increases, the higher the gate voltage spike and the wider the duration time. When $R_{\rm G}$ $=$ 100 $\Omega$, device A has a very high voltage spike about 1.85 V with a duration time of about 0.65 $\mu$s and the voltage spike is observed reducing to a very small value of about 0.4 V when $R_{\rm G}$ $=$ 3 $\Omega$, but at the same time the ringing starts rising rapidly as seen in Fig. 8. Device B and C have the same changing trend compared to device A, but it was obvious that device C has the lowest voltage spike, this is also due to the fact that device C has a different $C_{\rm GE}$ and $C_{\rm GC}$ compared to devices A and B.

However, we would like to point out that there could be a difference between the simulation results and experimental results due to the precision of the circuit model and the parameter dispersion of the IGBTs and other elements. Although the actual situation is much more complicated, this study still gives some insight for further improvement in the design. Nevertheless, the trends of the simulation results clearly agree with the experimental results.

4. Conclusion

This paper studies the d$V$/d$t$ induced voltage spike behavior, the relationship between this voltage spike and the d$V$/d$t$ rate, parasitic capacitances $C_{\rm GC}$, $C_{\rm GE}$ and gate resistance $R_{\rm G}$ is investigated theoretically, numerically and experimentally. An analytical formula describing the relationships between the voltage spike and d$V$/d$t$ rate, $C_{\rm GC}$, $C_{\rm GE}$ and $R_{\rm G}$ is derived. Based on the simulation results it has been verified that the voltage spike of the low-side IGBT that are caused by the d$V$/d$t$ is proportional to the d$V$/d$t$ rate, gate resistance $R_{\rm G}$ and gate-collector capacitance $C_{\rm GC}$ of the IGBT, but is inversely proportional to gate-emitter capacitance $C_{\rm GE}$ of the IGBT. This conclusion is also validated by the experiment on three IGBT samples, devices A, B and C. Take device A as an example, the voltage spike caused by the d$V$/d$t$ can be reduced by around 54% when the d$V$/d$t$ rate changes from 200 to 20 V/$\mu$s at $R_{\rm G}$ $=$ 100 $\Omega$. In addition, when d$V$/d$t$ $=$ 200 V/$\mu$s, decreasing $R_{\rm G}$ from 100 to 3 $\Omega$, a large reduction of voltage spike in the range of 79% is expected. Furthermore, since device C has a much lower $C_{\rm GC}$ and higher $C_{\rm GE}$ compared with device B, its voltage spike is 66% lower than devices B under the same conditions d$V$/d$t$ $=$ 200 V/$\mu$s, $R_{\rm G}$ $=$ 100 $\Omega$.

Therefore, with the appropriate optimization of these parameters the d$V$/d$t$ induced voltage spike can be effectively controlled and the research results of this paper could be used as practical guidance for the design of the IGBT and the IPM.