Analysis of the d<i>V</i>/d<i>t</i> effect on an IGBT gate circuit in IPM

Qing Hua; Zehong Li; Bo Zhang; Xiangjun Huang; Dekai Cheng

doi:10.1088/1674-4926/34/4/045001

J. Semicond. > 2013, Volume 34 > Issue 4 > 045001

SEMICONDUCTOR INTEGRATED CIRCUITS

Analysis of the dV/dt effect on an IGBT gate circuit in IPM

Qing Hua^1,, Zehong Li¹, Bo Zhang¹, Xiangjun Huang² and Dekai Cheng²

+ Author Affiliations

Corresponding author: Hua Qing, Email:huaqing2014@126.com

DOI: 10.1088/1674-4926/34/4/045001

Abstract: The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV/dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV/dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on. By optimizing these parameters, the dV/dt induced voltage spike can be effectively controlled.

Key words: IGBT, dV/dt, voltage spike, IPM

References

[1]	Ranstad P, Nee H P. On dynamic effects influencing IGBT losses in soft-switching converters. IEEE Trans Power Electron, 2011, 26(1):260 doi: 10.1109/TPEL.2010.2055581
[2]	Letor R, Aniceto G C. Short circuit behavior of IGBT's correlated to the intrinsic device structure and on the application circuit. IEEE Trans Industry Applications, 1995, 31(2):234 doi: 10.1109/28.370268
[3]	Park S, Jahns T M. Flexible dv/dt and di/dt control method for insulated gate power switches. IEEE Trans Industry Applications, 2003, 39(3):657 doi: 10.1109/TIA.2003.810654
[4]	Takizawa S, Igarashi S, Kuroki K. A new di/dt control gate drive circuit for IGBTs to reduce EMI noise and switching losses. IEEE PESC, 1998, 2:1443
[5]	Igarashi S, Takizawa S, Tabata M, et al. An active control gate drive circuit for IGBT's to realize low-noise and snubberless system. Proc ISPSD, 1997:69
[6]	Bryant A, Yang S, Mawby P, et al. Investigation into IGBT dV/dt during turn-off and its temperature dependence. IEEE Trans Power Electron, 2011, 26(10):3019 doi: 10.1109/TPEL.2011.2125803
[7]	Idir N, Bausiere R, Franchaud J J. Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors. IEEE Trans Power Electron, 2006, 21(4):849 doi: 10.1109/TPEL.2007.876895
[8]	Wu W, Held M, Umbricht N, et al. dv/dt induced latching failure in 1200 V/400 A halfbridge IGBT modules. IEEE IRPS, 1994:420 http://ieeexplore.ieee.org/document/307804/?reload=true&arnumber=307804&filter%3DAND(p_IS_Number:7501)
[9]	Murata K, Harada, K. Analysis of a self turn-on phenomenon on the synchronous rectifier in a DC-DC converter. INTELEC, 2004:199 http://ieeexplore.ieee.org/document/1252113/
[10]	Yedinak J, Gladish J, Brockway B, et al. A 600 V quick punch through (QPT) IGBT design concept for reducing EMI. Proc ISPSD, 2003:67
[11]	Musumeci S, Pagano R, Raciti A, et al. A novel protection technique devoted to the improvement of the short circuit ruggedness of IGBTs. IECON, 2003, 2:1733 http://ieeexplore.ieee.org/document/1280319/?arnumber=1280319

Fig. 1. Simplified circuit schematic of three-phase full-bridge inverter.

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Fig. 2. Photograph of the IPM.

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Fig. 3. Simulation-assisted circuit to analyze the d$V$/d$t$ performance.

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Fig. 4. Simulated voltage spike versus d$V$/d$t$ rate.

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Fig. 5. Simulated voltage spike versus $C_{\rm GC}$.

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Fig. 6. Simulated voltage spike versus $R_{\rm G}$.

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Fig. 7. Measured voltage spike versus d$V$/d$t$ rate of device A.

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Fig. 8. Measured voltage spike versus $R_{\rm G}$ of device A.

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Fig. 9. Measured voltage spike versus d$V$/d$t$ rate of device B.

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Fig. 10. Measured voltage spike versus $R_{\rm G}$ of device B.

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Fig. 11. Measured voltage spike versus d$V$/d$t$ rate of device C.

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Fig. 12. Measured voltage spike versus $R_{\rm G}$ of device C.

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Table 1. Device parameters.

[1]	Ranstad P, Nee H P. On dynamic effects influencing IGBT losses in soft-switching converters. IEEE Trans Power Electron, 2011, 26(1):260 doi: 10.1109/TPEL.2010.2055581
[2]	Letor R, Aniceto G C. Short circuit behavior of IGBT's correlated to the intrinsic device structure and on the application circuit. IEEE Trans Industry Applications, 1995, 31(2):234 doi: 10.1109/28.370268
[3]	Park S, Jahns T M. Flexible dv/dt and di/dt control method for insulated gate power switches. IEEE Trans Industry Applications, 2003, 39(3):657 doi: 10.1109/TIA.2003.810654
[4]	Takizawa S, Igarashi S, Kuroki K. A new di/dt control gate drive circuit for IGBTs to reduce EMI noise and switching losses. IEEE PESC, 1998, 2:1443
[5]	Igarashi S, Takizawa S, Tabata M, et al. An active control gate drive circuit for IGBT's to realize low-noise and snubberless system. Proc ISPSD, 1997:69
[6]	Bryant A, Yang S, Mawby P, et al. Investigation into IGBT dV/dt during turn-off and its temperature dependence. IEEE Trans Power Electron, 2011, 26(10):3019 doi: 10.1109/TPEL.2011.2125803
[7]	Idir N, Bausiere R, Franchaud J J. Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors. IEEE Trans Power Electron, 2006, 21(4):849 doi: 10.1109/TPEL.2007.876895
[8]	Wu W, Held M, Umbricht N, et al. dv/dt induced latching failure in 1200 V/400 A halfbridge IGBT modules. IEEE IRPS, 1994:420 http://ieeexplore.ieee.org/document/307804/?reload=true&arnumber=307804&filter%3DAND(p_IS_Number:7501)
[9]	Murata K, Harada, K. Analysis of a self turn-on phenomenon on the synchronous rectifier in a DC-DC converter. INTELEC, 2004:199 http://ieeexplore.ieee.org/document/1252113/
[10]	Yedinak J, Gladish J, Brockway B, et al. A 600 V quick punch through (QPT) IGBT design concept for reducing EMI. Proc ISPSD, 2003:67
[11]	Musumeci S, Pagano R, Raciti A, et al. A novel protection technique devoted to the improvement of the short circuit ruggedness of IGBTs. IECON, 2003, 2:1733 http://ieeexplore.ieee.org/document/1280319/?arnumber=1280319

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Received: 13 August 2012 Revised: 23 October 2012 Online: Published: 01 April 2013

The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV/dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV/dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on. By optimizing these parameters, the dV/dt induced voltage spike can be effectively controlled.

Analysis of the dV/dt effect on an IGBT gate circuit in IPM

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