Fig. 1.
Simplified circuit schematic of three-phase full-bridge inverter.
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| Citation: |
Qing Hua, Zehong Li, Bo Zhang, Xiangjun Huang, Dekai Cheng. Analysis of the dV/dt effect on an IGBT gate circuit in IPM[J]. Journal of Semiconductors, 2013, 34(4): 045001. doi: 10.1088/1674-4926/34/4/045001
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Q Hua, Z H Li, B Zhang, X J Huang, D K Cheng. Analysis of the dV/dt effect on an IGBT gate circuit in IPM[J]. J. Semicond., 2013, 34(4): 045001. doi: 10.1088/1674-4926/34/4/045001.
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Analysis of the dV/dt effect on an IGBT gate circuit in IPM
DOI: 10.1088/1674-4926/34/4/045001
More Information
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Abstract
The effect of dV/dt on the IGBT gate circuit in IPM is analyzed both by simulation and experiment. It is shown that a voltage slope applied across the collector-emitter terminals of the IGBT can induce a gate voltage spike through the feedback action of the parasitic capacitances of the IGBT. The dV/dt rate, gate-collector capacitance, gate-emitter capacitance and gate resistance have a direct influence on this voltage spike. The device with a higher dV/dt rate, gate-collector capacitance, gate resistance and lower gate-emitter capacitance is more prone to dV/dt induced self turn-on. By optimizing these parameters, the dV/dt induced voltage spike can be effectively controlled.-
Keywords:
- IGBT,
- dV/dt,
- voltage spike,
- IPM
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References
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