Citation: |
Zuozhen Fu, Huaxiang Yin, Xiaolong Ma, Shumin Chai, Jianfeng Gao, Dapeng Chen. Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices[J]. Journal of Semiconductors, 2013, 34(6): 066002. doi: 10.1088/1674-4926/34/6/066002
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Z Z Fu, H X Yin, X L Ma, S M Chai, J F Gao, D P Chen. Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices[J]. J. Semicond., 2013, 34(6): 066002. doi: 10.1088/1674-4926/34/6/066002.
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Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices
DOI: 10.1088/1674-4926/34/6/066002
More Information
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Abstract
The optimizations to metal gate structure and film process were extensively investigated for great metal-gate stress (MGS) in 20 nm high-k/metal-gate-last (HK/MG-last) nMOS devices. The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values (0 to-6 GPa) was implemented in the device simulation along with other traditional process-induced-strain (PIS) technologies like e-SiC and nitride capping layer. The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down. In addition, the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated. Also with a new method of fully stressed replacement metal gate (FSRMG) and using plane-shape-HfO to substitute U-shape-HfO, the effect of MGS was improved. For greater film stress in the metal gate, the process conditions for physical vapor deposition (PVD) TiNx were optimized. The maximum compressive stress of-6.5 GPa TiNx was achieved with thinner film and greater RF power as well as about 6 sccm N ratio.-
Keywords:
- metal gate stress,
- 20 nm CMOS devices,
- high-k/metal gate,
- PVD,
- TiNx
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References
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