Citation: |
Haimeng Huang, Xingbi Chen. New expressions for non-punch-through and punch-through abrupt parallel-plane junctions based on Chynoweth law[J]. Journal of Semiconductors, 2013, 34(7): 074003. doi: 10.1088/1674-4926/34/7/074003
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H M Huang, X B Chen. New expressions for non-punch-through and punch-through abrupt parallel-plane junctions based on Chynoweth law[J]. J. Semicond., 2013, 34(7): 074003. doi: 10.1088/1674-4926/34/7/074003.
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New expressions for non-punch-through and punch-through abrupt parallel-plane junctions based on Chynoweth law
DOI: 10.1088/1674-4926/34/7/074003
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Abstract
The relations among the breakdown voltage, the width and the concentration of the voltage-sustaining layer for the non-punch-through (NPT) and punch-through (PT) abrupt parallel-plane junctions have been re-established based on the ionization integral by the Chynoweth model, distinguished from the conventional results obtained by the Fulop model. The numerical calculation results indicate that the new expressions are more accurate than those in previous literature. While the breakdown voltage of the NPT case varied from 400 to 1600 V using the Chynoweth model, the value using the Fulop model is overestimated by 12% (478 V) to 18% (1895 V). For the PT case with optimum design of the specific on-resistance, when the breakdown voltage is varied from 400 to 1600 V, the width and concentration are from 81.0168% to 80.2416% and from 91.4341% to 91.6941% of those of the NPT cases, respectively. The relations between the specific on-resistance and the breakdown voltage for both the NPT and PT structures are also established. Simulation results by MEDICI show good agreement with the proposed expressions. -
References
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