1. Introduction

The continuous scaling of metal-oxide-semiconductor (MOS) transistors makes it imperative to replace the conventional SiO₂/poly-Si structure with high-$k$ dielectric/metal gate stack^[1-3]. The integration of high-$k$ dielectric/metal gate stack into MOS transistor, however, faces challenges such as threshold voltage (${V_{{\text{th}}}}$) control. Generally, band edge metal gates are needed to obtain low ${V_{{\text{th}}}}$ for bulk CMOS application^[4]. Among all the potential candidates for metal gate, TiN is widely studied because of its superior performance such as stability when contacted with high-$k$ dielectrics, low resistivity, and process compatibility^{[5, 6]}. However, the EWF of TiN lies at the mid-gap of silicon or beyond. Modulating the EWF of a TiN metal gate to meet the NMOS requirement is of interest, and Al incorporation is considered promising^[7]. However, for gate-last integration scheme, a low thermal budget is necessary. So finding appropriate Al incorporation conditions suitable for gate-last integration is important. In this work, capacitors with W/TiN/Al/TiN gate stacks were fabricated to investigate the effect of Al incorporation and low temperature annealing on the EWF of TiN.

2. Experimental

Firstly, 10 nm SiO₂ films were thermally grown on diluted-HF last P type Si wafers (1.34 $\times$ 10¹⁵ cm^-3), and then the thick SiO₂ films were wet etched to have a terraced structure. Then two sets of samples were fabricated with W 100 nm/TiN 15 nm/Al 5 nm/TiN 10 nm and W 100 nm/TiN 20 nm/Al 5 nm/TiN 5 nm stacks deposited on the terraced SiO₂ $in$-$situ$ in ULVAC-2306, respectively. A control sample with W 100 nm/TiN 30 nm was also prepared. Then, after back oxide removal, Al metallization and forming gas annealing (FGA) (380 ℃, 20 min, NO₂ : HO₂ $=$ 10 : 1) were performed. And then all samples underwent various annealing conditions, which are collectively named as post-metal annealing (PMA) in the present work. PMA was performed in NO₂ ambience at atmosphere pressure. Furthermore, capacitors with atomic layer deposited (ALD) HfO₂ dielectrics were also fabricated to confirm the effect of Al incorporation on the EWF of, TiN. 2.97 nm thick HfO₂ films, whose thickness was calibrated from the X-ray reflection spectrum, were deposited on the diluted-HF last P type Si wafers using TEMAHf as precursor and HO₂O as oxidant respectively, which was finished at 300 ℃ in TFS200. And metal gate conditions will be discussed in detail in the subsequent section. The $C$-$V$ characteristics of the capacitors were measured at a frequency of 1 MHz with MDC 7200 and fitted with QMCV model.

3. Results and discussion

For capacitors with a terraced SiO₂ structure, the relationship of flat band voltage (V_fb) versus equivalent oxide thickness (EOT) is expressed by

$${V_{{\text{fb}}}} = {\phi _{{\text{ms}}}} - {Q_{{\text{Si}}{{\text{O}}_{\text{2}}}, {\kern 1pt} {\text{Si}}}}{\text{EOT}}/{\varepsilon _0}{\varepsilon _{{\text{Si}}{{\text{O}}_{\text{2}}}}},$$

(1)

where $\phi$_ms is the work function difference between the metal gate ($\phi$_m) and Si substrate ($\phi$_s). $Q$_{SiO2, Si} is the areal charge densities (per unit area) at SiO₂/Si interface. $\varepsilon_0$ and $\varepsilon$ SiO₂ express the vacuum permittivity and the relative permittivity of SiO₂, respectively. The EWF of the metal gate can be obtained from $\phi$ s plus $\phi$ ms. The work function of Si substrate ($\phi$_s) in this work is calculated to be 4.91 eV.

V_fb-EOT curves for samples with terraced SiO₂ structures which undergo FGA only are shown in Fig. 1. As shown in Fig. 1, the EWF of TiN metal gate without Al incorporation is 4.48 eV. The EWF of metal gates with Al incorporation are 4.46 eV and 4.36 eV for samples with 10 nm bottom TiN and 5 nm bottom TiN respectively. The sample with 5 nm bottom TiN shows more negative $\phi$ ms shift while the sample with 10 nm bottom TiN shows tiny $\phi$ ms shift. The phenomenon is in good agreement with our previous work that only about 10 nm thickness of metal gate on a high-k dielectric plays the role as work function layer. It is obvious that a bottom TiN layer with 10 nm is thick enough to screen the effect of Al on the work function. However, the result of the sample with 5 nm bottom TiN shows the competence of Al to modulate the work function of TiN metal gate because of its lower work function. So it is important to select an appropriate bottom TiN thickness for the application of Al incorporation.

It is considered that PMA can affect the modulating ability of Al. This is because PMA is an effective method to drive the Al downward, which further affects the work function of TiN metal gate. So different PMA conditions are imposed on all samples to investigate the effect of PMA on the EWF of metal gates. The results are shown in Fig. 2. Figure 2(a) shows the V_fb-EOT relationships of a sample without Al. As shown in Fig. 2(a), the $\phi$ ms shows a slight shift due to thermal annealing which testifies the good thermal stability of the TiN metal gate. The V_fb-EOT relationships of the sample with 5 nm Al and 10 nm bottom TiN are shown in Fig. 2(b). As shown in Fig. 2(b), when the sample is annealed at 450 ℃ for 30 s, the $\phi$ ms is almost the same as that without PMA. However, when additional annealing at 470 ℃ for 30 s is exerted, the $\phi$ ms significantly shifts by as much as 130 meV and the $\phi$ ms is further decreased by another annealing at 500 ℃ for 30 s. After the total annealing, the $\phi$ ms negatively shifts by as much as 210 meV, and the EWF of the metal gate is 4.25 eV. Figure 2(c) shows the V_fb-EOT relationships of the sample with Al and 5 nm bottom TiN. From Fig. 2(c), the same tendency of $\phi$ ms shift is observed. And the EWF of the metal gate is 4.19 eV, which is lower than the sample with a 10 nm bottom TiN layer. Also from Figs. 2(b) and 2(c), it can be found that there is a threshold of PMA to make the Al diffuse.

From the discussion above, we can conclude that Al incorporation is an effective approach to modulate the EWF of TiN metal gate; higher PMA temperature makes more negative shift and a thicker bottom TiN layer blocks the diffusion of Al. The crux of Al incorporation is to select an appropriate Al/TiN ratio and PMA condition. In order to confirm the effect of Al incorporation on the EWF of a TiN metal gate when the EOT is below 1 nm and provide practicable conditions for NMOS, capacitors with 2.97 nm ALD-HfO₂ were fabricated and the EOT of all samples are fitted to be less than 1 nm. And V_fb is employed to indicate the effect of Al incorporation on the EWF of a metal gate.

Figure 3 shows the $C$-$V$ plots of the samples with W 100 nm/TiN 20 nm/Al 5 nm/TiN 5 nm/ALD-HfO₂ 2.97 nm/Si structure undergoing different PMA conditions. The $C$-$V$ curve of the sample without Al with FGA only is also shown as reference. As shown in Fig. 3, the EOT of all samples are below 1 nm. And also as shown in Fig. 3, the negative shift of V_fb can be observed as much as 270 mV, which confirm the EWF modulating competence of Al incorporation. But we can also see from the plot that there is a critical temperature, if the thermal process is higher than it, the $\phi$ ms will shift positively. This may result from the Al diffusing into the HfO₂ film and forming the dipole at HfO₂/SiO₂ interface. And another notable point is that the threshold of driving Al diffusing is lower than that discussed above. The effect of HfO₂ can be excluded because the V_fb of sample with W/TiN/HfO₂ structure shows no response to PMA up to 470 ℃ according to our previous work. And we can find that the work function of TiN metal gate here is about 4.7 eV which is higher than that used above. The difference of TiN layer may result in different diffusivity of Al. Also as shown in Fig. 3, EOT decreases as PMA temperature increases which is attributed to oxygen scavenging due to Al incorporation.

In order to select an optimized condition more suitable for NMOS. The thickness of the bottom TiN layer is further decreased. A capacitor with W 100 nm/TiN 23 nm/Al 4 nm/TiN 3 nm/ALD-HfO₂ 2.97 nm gate stack was fabricated. Figure 4 shows the $C$-$V$ plots of the samples. By appropriate annealing, as much as 410 mV V_fb shift can be obtained, which is more suitable for NMOS. And positive shift of V_fb can also be seen from Fig. 4 when annealed at 370 ℃ for 60 s.

It is important to confirm the feasibility of EWF modulation by Al incorporation from the viewpoint of CMOS integration. In order to achieve this purpose, a sample with annealing suitable for PMOS was fabricated. The detailed process flow is as follows: after 2.97 nm HfO₂ deposition on the HF-last substrate, post deposition annealing (PDA) at 470 ℃ for 15 s at NO₂ with traces of O₂ ambience was performed. And then 3 nm TiN was deposited followed by 450 ℃ 60 s annealing with the same ambience as PDA. Such annealing can make V_fb positive shift which is more suitable for PMOS (not shown here). Then W 100 nm/TiN 23 nm/Al 4 nm was capped. Backside metallization and FGA (380, 20 min, NO₂ : HO₂ $=$ 10 : 1) were also imposed. Figure 5 shows the $C$-$V$ plots of the sample with different PMA conditions. Significant V_fb shift prove the feasibility of EWF modulation by Al incorporation. And compared with the sample without PDA and PMA, the enhanced effect of Al on work function can also be observed. When annealed at 370 ℃ for 30 s, the V_fb shift of the sample with PDA and PMA is 380 meV, while that for the sample without PDA and PMA is 120 meV. And PMA can change the work function of a TiN metal gate. This further proves the supposition that a different TiN layer may result in different diffusivity of Al.

4. Conclusions

We have systematically studied the impact of Al incorporation on the EWF of a TiN metal gate with terraced-SiO$_2$ and ALD-HfO₂ as dielectrics respectively, and find that Al incorporation makes the EWF of TiN shift toward the conduction band of Si significantly. The Al/TiN thickness ratio and PMA conditions have a significant influence on the work function modulation of Al incorporation. Appropriate conditions are given in present work which can be used in NMOS devices.