1. Introduction
Between 1993 and 2005 the adiabatic switching was popular as an ultra-low-power circuit technique to design digital VLSI circuits. However, at the nanoscale, the area overhead and the slow speed of the adiabatic logic became a matter of concern. Various types of low-power circuit techniques were proposed for better performance in terms of the power delay product (PDP) and power area, and most of them were based on compromises over the supply voltage, switching activity and load capacitance. Supply voltage scaling has power-efficient digital circuits, but beyond sub-100 nm technology it is hard to employ supply voltage scaling for low-power digital VLSI circuits. Therefore, the adiabatic switching technique may now be a better option to achieve ultra-low-power digital CMOS logic. This technique can be most favorable in low-power applications, such as bio-medical, space, robotics, portable electronic and deep-sea devices, where conventional energy is limited or not available and speed is not critical. Adiabatic switching is a straightforward low-power circuit technique because there is no need to compromise the supply voltage, switching activity or load capacitance of the circuit.
In the last few years, numerous adiabatic circuit families have been investigated, and adiabatic low-power CMOS digital circuit applications that show significant energy savings have been fabricated[1-8]. Adiabatic switching is based on slow charging of the circuit nodes, recovering the energy from the charged nodes, and reutilizing the recovered energy[9]. In order to slowly charge the capacitive nodes, the adiabatic switching technique uses a clocked pulsed or AC power.
We carried out an extensive comparative study of conventional CMOS logic and adiabatic logic under scaling of the design and device parameters, which explore the workability and the merits of adiabatic switching. For this purpose, we introduced an analytical model that estimates the energy loss in adiabatic logic with scaling device and design parameters. The results obtained from the model are used to validate the simulation results. The proposed model is based on RC linearization[10, 11] of the adiabatic inverter/buffer gate shown in Fig. 1[9], and the equivalent resistance value of a transmission gate can be determined by considering the linear mode of conduction of PMOS and NMOS FETs. However, the equivalent resistance of a transmission gate is independent of the output voltage and remains relatively constant in one of the following conduction mode combinations of the transistors: (1) NMOS and PMOS are in saturation, (2) NMOS is in saturation and PMOS is linear, and (3) NMOS is in cutoff and PMOS is linear[12].

We develop the energy estimation model for n-input adiabatic gates by considering the following facts.
(1) The on-resistance
(2) The device may be conducted in saturation mode.
We applied the proposed energy estimation model to study the scaling trends in an adiabatic gate. The supply voltage and device parameters, such as threshold voltage and oxide thickness, are scaled to prove the utility of adiabatic logic at the nanoscale.
The rest of the paper is organized as follows. Section 2 models the energy estimation for an adiabatic logic gate. In Section 3, the simulation, model results and scaling trends are discussed. Finally, concluding remarks are made in Section 4.
2. Proposed energy estimation model
2.1 Energy consumption
The fundamental adiabatic buffer/inverter[9] circuit is shown in Fig. 1. It consists of transmission gates to form the switching network for logical functionality and a ramp power supply clock
We determined the equivalent resistance of the transmission gate with a change in the transit time of the ramp power supply clock. The output conductance of the n-device can be written as:
gn=∂Ids∂Vds=∂Ids∂VΦ=∂{kn[(Vgs−Vth,n)Vds−V2ds2]}∂Vds=kn[(Vgs−Vth,n)−Vds],0<Vds⩽ |
(1) |
where subscripts n and p denote the n-device and p-device, respectively.
In the adiabatic inverter gate, since the
\begin{equation} \begin{split} g_{\rm n} {}& =k_{\rm n} \left(V_{\rm gs}-V_{\mathit{\Phi }}-V_{\rm th, n}\right), \quad V_{\mathit{\Phi }} \leqslant V_{\rm dd}-V_{\rm th, n}, \\[2mm]& =0, \quad V_{\mathit{\Phi }} > V_{\rm dd}-V_{\rm th, n}. \end{split} \end{equation} |
(2) |
\begin{equation} \begin{split} g_{\rm n, avg} {}& =\frac{1}{T} \int^T_0 g_{\rm n} {\rm d} t \\[2mm]& =\frac{1}{V_{\rm dd}} \int^{V_{\rm dd}}_0 -V_{\rm th, n}k_{\rm n} \left(V_{\rm dd}-V_{\mathit{\Phi }}-V_{\rm th, n}\right) {\rm d} V_{\mathit{\Phi }} \\[2mm]& =\frac{k_n}{2V_{\rm dd}}\left(V_{\rm dd}-V_{\rm th, n}\right)^2. \end{split} \end{equation} |
(3) |
The on-resistance of the n-device with a change in ramp power supply can be written as:
\begin{equation} R_{\rm n}=\frac{2V_{\rm dd}}{k_{\rm n} \left(V_{\rm dd}-V_{\rm th, n} \right)^2}. \end{equation} |
(4) |
Similarly, the on-resistance of the p-device with a change in ramp power supply would be:
\begin{equation} R_{\rm p}=\frac{2V_{\rm dd}}{k_{\rm p} \left( V_{\rm dd}-\vert V_{\rm th, p}\vert \right)^2}. \end{equation} |
(5) |
If
\begin{equation} R_{\rm eq}=R_{\rm p}\vert \vert R_{\rm n}=\frac{V_{\rm dd}}{k\left( V_{\rm dd}-V_{\rm th} \right)^2}. \end{equation} |
(6) |
Since throughout the change in output voltage, the equivalent resistance of a TG remains unchanged as the devices conduct in either conduction mode[12]. Hence, even if the saturation current equations are directly applied to the on-resistances:
The ramp power supply clock
\begin{equation} E_{\rm adia}=PT=I^2 R_{\rm eq} T = \left(\frac{CV_{\rm dd}}{T} \right)^2 R_{\rm eq}T, \end{equation} |
(7) |
where
\begin{equation} E_{\rm adia}=\frac{2\xi C^2V^2_{\rm dd}R_{\rm eq}}{T}=\frac{2\xi C^2V^3_{\rm dd}}{Tk \left(V_{\rm dd}-V_{\rm th} \right)^2}, \end{equation} |
(8) |
where
2.2 Scaling trends model
The analysis of the energy performance of an adiabatic logic gate is carried out by scaling the device and design parameters. The device scaling-dependent coefficients are extracted from the above expressions, which can affect the energy performance of an adiabatic gate. From Eq. (6), the RC time constant of a TG switch can be written as:
\begin{equation} \begin{split} R_{\rm eq}C_{\rm OX} {}& =\frac{V_{\rm dd}}{\mu \left( \dfrac{1}{WL}\right)\dfrac{W}{L}\left(V_{\rm dd}-V_{\rm th} \right)^2} \\[2mm]& =\frac{L^2V_{\rm dd}}{\mu \left(V_{\rm dd}-V_{\rm th}\right)^2} \\[2mm]& =\tau_{\rm adia}. \end{split} \end{equation} |
(9) |
Here,
\begin{equation} \begin{split} E_{\rm adia}{}& =\frac{2 \xi C^2V^2_{\rm dd}R_{\rm eq}}{T}=\frac{2\xi C^2V^3_{\rm dd}}{Tk\left(V_{\rm dd}-V_{\rm th}\right)^2} \\[2mm]& =\frac{2\xi V^2_{\rm dd}\left(1+\dfrac{C_{\rm L}}{C_{\rm int}} \right)^2C_{\rm int}}{T_{\rm norm}}, \end{split} \end{equation} |
(10) |
where
\begin{equation} T_{\rm norm}=\frac{TC_{\rm ox}}{\tau_{\rm adia}C_{\rm int}} \end{equation} |
(11) |
is defined as the normalized transit time depending on the design and technology parameters. Thus, the average energy consumption of the n-input adiabatic gate can easily be evaluated by scaling the design and technology parameters. Equations (10) and (11) help us to study the scaling effects on the energy performance of adiabatic logic, and a comparative study of the scaling trends between adiabatic logic and conventional CMOS logic has been carried out.
3. Results and discussion
A study of the scaling trends enables better circuit design. Scaling trends in an adiabatic logic gate are studied at the 90 nm and 65 nm technology nodes. The model expressions derived in Section 2 are applied to study the scaling trends, and simulations are performed to evaluate and compare the energy performance of adiabatic and conventional CMOS logic gates. The energy loss of the extracted terms
Simulation set-up: the model and simulation results are observed at an operating frequency of 250 MHz and a load capacitance of
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In a VLSI circuit, the selection of the device threshold voltage depends on the performance, and the multi-threshold voltage for a device can be chosen. The device with a high threshold voltage has high on-resistance due to low over-drive voltage
The supply voltage scaling trends for both the adiabatic and conventional CMOS inverter gates are shown in Fig. 2(b). We applied the supply voltage range from 0.7 to 1.4 V at an operating frequency equal to 250 MHz and load capacitance
Finally, the energy performances are studied against the scaling of device gate oxide thickness
We also observed the scaling trends at the 65 nm CMOS technology node. Figures 3(a), 3(b) and 3(c) show the energy performance against the scaling of the
Our motivation behind this work is to present a straightforward procedure for examining the scaling trends in adiabatic logic. The leakage power was not incorporated to derive a simple analytical model for investigating the scaling trends in adiabatic logic gates, hence minor validation error is observed in the results.
4. Conclusions
In this paper we have proposed an analytical model to estimate the energy performance of an adiabatic logic gate. To explore the importance of adiabatic logic at the nanoscale, the energy performance against the scaling of various device/design parameters has been analyzed and discussed. Extensive comparative analysis has been carried out at 90 nm and 65 nm CMOS technology nodes, and we attempted to prove that adiabatic switching is a straightforward low-power circuit technique at nanoscale CMOS technology. The validation results have proved that the proposed model is suitable for designing robust ultra-low-power adiabatic logic circuits.