1. Introduction

Between 1993 and 2005 the adiabatic switching was popular as an ultra-low-power circuit technique to design digital VLSI circuits. However, at the nanoscale, the area overhead and the slow speed of the adiabatic logic became a matter of concern. Various types of low-power circuit techniques were proposed for better performance in terms of the power delay product (PDP) and power area, and most of them were based on compromises over the supply voltage, switching activity and load capacitance. Supply voltage scaling has power-efficient digital circuits, but beyond sub-100 nm technology it is hard to employ supply voltage scaling for low-power digital VLSI circuits. Therefore, the adiabatic switching technique may now be a better option to achieve ultra-low-power digital CMOS logic. This technique can be most favorable in low-power applications, such as bio-medical, space, robotics, portable electronic and deep-sea devices, where conventional energy is limited or not available and speed is not critical. Adiabatic switching is a straightforward low-power circuit technique because there is no need to compromise the supply voltage, switching activity or load capacitance of the circuit.

In the last few years, numerous adiabatic circuit families have been investigated, and adiabatic low-power CMOS digital circuit applications that show significant energy savings have been fabricated^[1-8]. Adiabatic switching is based on slow charging of the circuit nodes, recovering the energy from the charged nodes, and reutilizing the recovered energy^[9]. In order to slowly charge the capacitive nodes, the adiabatic switching technique uses a clocked pulsed or AC power.

We carried out an extensive comparative study of conventional CMOS logic and adiabatic logic under scaling of the design and device parameters, which explore the workability and the merits of adiabatic switching. For this purpose, we introduced an analytical model that estimates the energy loss in adiabatic logic with scaling device and design parameters. The results obtained from the model are used to validate the simulation results. The proposed model is based on RC linearization^{[10, 11]} of the adiabatic inverter/buffer gate shown in Fig. 1^[9], and the equivalent resistance value of a transmission gate can be determined by considering the linear mode of conduction of PMOS and NMOS FETs. However, the equivalent resistance of a transmission gate is independent of the output voltage and remains relatively constant in one of the following conduction mode combinations of the transistors: (1) NMOS and PMOS are in saturation, (2) NMOS is in saturation and PMOS is linear, and (3) NMOS is in cutoff and PMOS is linear^[12].

We develop the energy estimation model for n-input adiabatic gates by considering the following facts.

(1) The on-resistance $R$ of an MOSFET switch of the transmission gate (TG) changes with the change in the ramp power supply clock.

(2) The device may be conducted in saturation mode.

We applied the proposed energy estimation model to study the scaling trends in an adiabatic gate. The supply voltage and device parameters, such as threshold voltage and oxide thickness, are scaled to prove the utility of adiabatic logic at the nanoscale.

The rest of the paper is organized as follows. Section 2 models the energy estimation for an adiabatic logic gate. In Section 3, the simulation, model results and scaling trends are discussed. Finally, concluding remarks are made in Section 4.

2. Proposed energy estimation model

2.1 Energy consumption

The fundamental adiabatic buffer/inverter^[9] circuit is shown in Fig. 1. It consists of transmission gates to form the switching network for logical functionality and a ramp power supply clock $V_{\mathit{\Phi }}$ of maximum amplitude $V_{\rm dd}$ and transition time $T$. With the application of inputs and the power clock $V_{\mathit{\Phi }}$, the transmission gates transfer logic '1' or '0'. The output node voltage follows $V_{\mathit{\Phi }}$ from 0 to $V_{\rm dd}$ and vice-versa. The equivalent resistance of a TG is the parallel combination of the resistances of the n-device and p-device.

We determined the equivalent resistance of the transmission gate with a change in the transit time of the ramp power supply clock. The output conductance of the n-device can be written as:

$\begin{equation} \begin{split} g_{\rm n}{}& =\frac{\partial I_{\rm ds}}{\partial V_{\rm ds}}=\frac{\partial I_{\rm ds}}{\partial V_{\mathit{\Phi }}} =\frac{\partial \left\{ k_{\rm n}\left[\left(V_{\rm gs}-V_{\rm th, n} \right)V_{\rm ds}-\dfrac{V_{\rm ds}^2}{2} \right]\right\}}{\partial V_{\rm ds}} \\[3mm] & =k_{\rm n}\left[\left(V_{\rm gs}-V_{\rm th, n} \right)-V_{\rm ds}\right], \quad 0 < V_{\rm ds} \leqslant V_{\rm gs}-V_{\rm th, n}, \end{split} \end{equation}$

(1)

where subscripts n and p denote the n-device and p-device, respectively. $I_{\rm ds}$ is the drain current of the device, and $V_{\rm ds}$ and $V_{\rm gs}$ are the drain and gate voltage, respectively. $V_{\rm th}$ is the device threshold voltage, and $k_{\rm n}$ is the device trans-conductance parameter.

In the adiabatic inverter gate, since the $V_{\rm ds}$ of the conducting device follows the power supply clock $V_{\mathit{\Phi }}$, the conductance of the n-device can therefore be written as:

$\begin{equation} \begin{split} g_{\rm n} {}& =k_{\rm n} \left(V_{\rm gs}-V_{\mathit{\Phi }}-V_{\rm th, n}\right), \quad V_{\mathit{\Phi }} \leqslant V_{\rm dd}-V_{\rm th, n}, \\[2mm]& =0, \quad V_{\mathit{\Phi }} > V_{\rm dd}-V_{\rm th, n}. \end{split} \end{equation}$

(2)

$V_{\rm dd}$ is the maximum amplitude of the power clock signal and $V_{\rm gs}$. The average conductance is then determined as follows:

$\begin{equation} \begin{split} g_{\rm n, avg} {}& =\frac{1}{T} \int^T_0 g_{\rm n} {\rm d} t \\[2mm]& =\frac{1}{V_{\rm dd}} \int^{V_{\rm dd}}_0 -V_{\rm th, n}k_{\rm n} \left(V_{\rm dd}-V_{\mathit{\Phi }}-V_{\rm th, n}\right) {\rm d} V_{\mathit{\Phi }} \\[2mm]& =\frac{k_n}{2V_{\rm dd}}\left(V_{\rm dd}-V_{\rm th, n}\right)^2. \end{split} \end{equation}$

(3)

The on-resistance of the n-device with a change in ramp power supply can be written as:

$\begin{equation} R_{\rm n}=\frac{2V_{\rm dd}}{k_{\rm n} \left(V_{\rm dd}-V_{\rm th, n} \right)^2}. \end{equation}$

(4)

Similarly, the on-resistance of the p-device with a change in ramp power supply would be:

$\begin{equation} R_{\rm p}=\frac{2V_{\rm dd}}{k_{\rm p} \left( V_{\rm dd}-\vert V_{\rm th, p}\vert \right)^2}. \end{equation}$

(5)

If $V_{\rm th, n}=\vert V_{\rm th, p} \vert$ $=$ $V_{\rm th}$ and process trans-conductance gain $k_{\rm n}= k_{\rm p}$ $=$ $k$, then $R_{\rm eq}$ of the transmission gate can be written as:

$\begin{equation} R_{\rm eq}=R_{\rm p}\vert \vert R_{\rm n}=\frac{V_{\rm dd}}{k\left( V_{\rm dd}-V_{\rm th} \right)^2}. \end{equation}$

(6)

Since throughout the change in output voltage, the equivalent resistance of a TG remains unchanged as the devices conduct in either conduction mode^[12]. Hence, even if the saturation current equations are directly applied to the on-resistances: $R = V_{\rm ds}/I_{\rm ds}$ of the n-device and p-device, then the equivalent resistance of a TG would be the same as the expression given by Eq. (6).

The ramp power supply clock $V_{\mathit{\Phi }}$ delivers the charge $CV_{\rm dd}$ over a transit time period $T$, so the energy consumed by the switch resistance of a transmission gate (Fig. 1) would be^[9]:

$\begin{equation} E_{\rm adia}=PT=I^2 R_{\rm eq} T = \left(\frac{CV_{\rm dd}}{T} \right)^2 R_{\rm eq}T, \end{equation}$

(7)

where $C$ is the sum of the intrinsic capacitance of the transmission gate and the load capacitance, i.e. $C=C_{\rm int}+C_{\rm L}$. The intrinsic capacitance is extracted from the layout simulation, and at the 90 nm technology node it amounts to 0.5 fF, since the same amount of energy is consumed by an adiabatic gate during the ramp up (evaluation phase) and ramp down (recovery phase) of $V_{\mathit{\Phi }}$. Therefore, for a switching event (the sum of the evaluation phase and recovery phase), the energy consumption can be estimated using Eqs. (6) and (7):

$\begin{equation} E_{\rm adia}=\frac{2\xi C^2V^2_{\rm dd}R_{\rm eq}}{T}=\frac{2\xi C^2V^3_{\rm dd}}{Tk \left(V_{\rm dd}-V_{\rm th} \right)^2}, \end{equation}$

(8)

where $\xi$ is a constant shape factor (for linear ramp voltage $\xi$ $\approx$ 1)^[9].

2.2 Scaling trends model

The analysis of the energy performance of an adiabatic logic gate is carried out by scaling the device and design parameters. The device scaling-dependent coefficients are extracted from the above expressions, which can affect the energy performance of an adiabatic gate. From Eq. (6), the RC time constant of a TG switch can be written as:

$\begin{equation} \begin{split} R_{\rm eq}C_{\rm OX} {}& =\frac{V_{\rm dd}}{\mu \left( \dfrac{1}{WL}\right)\dfrac{W}{L}\left(V_{\rm dd}-V_{\rm th} \right)^2} \\[2mm]& =\frac{L^2V_{\rm dd}}{\mu \left(V_{\rm dd}-V_{\rm th}\right)^2} \\[2mm]& =\tau_{\rm adia}. \end{split} \end{equation}$

(9)

Here, $\tau_{\rm adia}$ is a scaling-dependent parameter and defined as the time taken by charge carriers to drift across the channel. The charging or transit time of the power clock ($T$) of the adiabatic gate must be $T$ $\gg$ $\tau _{\rm adia}$ to achieve the energy advantage of adiabatic switching over conventional CMOS logic. By using Eqs. (8) and (9), the energy consumption for an adiabatic buffer/inverter can be obtained as follows:

$\begin{equation} \begin{split} E_{\rm adia}{}& =\frac{2 \xi C^2V^2_{\rm dd}R_{\rm eq}}{T}=\frac{2\xi C^2V^3_{\rm dd}}{Tk\left(V_{\rm dd}-V_{\rm th}\right)^2} \\[2mm]& =\frac{2\xi V^2_{\rm dd}\left(1+\dfrac{C_{\rm L}}{C_{\rm int}} \right)^2C_{\rm int}}{T_{\rm norm}}, \end{split} \end{equation}$

(10)

where

$\begin{equation} T_{\rm norm}=\frac{TC_{\rm ox}}{\tau_{\rm adia}C_{\rm int}} \end{equation}$

(11)

is defined as the normalized transit time depending on the design and technology parameters. Thus, the average energy consumption of the n-input adiabatic gate can easily be evaluated by scaling the design and technology parameters. Equations (10) and (11) help us to study the scaling effects on the energy performance of adiabatic logic, and a comparative study of the scaling trends between adiabatic logic and conventional CMOS logic has been carried out.

3. Results and discussion

A study of the scaling trends enables better circuit design. Scaling trends in an adiabatic logic gate are studied at the 90 nm and 65 nm technology nodes. The model expressions derived in Section 2 are applied to study the scaling trends, and simulations are performed to evaluate and compare the energy performance of adiabatic and conventional CMOS logic gates. The energy loss of the extracted terms $E_{\rm adia}$ (Eq. (10)) and normalized transit time $T_{\rm norm}$ (Eq. (11)) are applied to predict the scaling trends for an adiabatic gate.

Simulation set-up: the model and simulation results are observed at an operating frequency of 250 MHz and a load capacitance of $C_{\rm L}$ $=$ 10 fF, and the process parameters are specified in Table 1. The supply voltage $V_{\rm dd}$ $=$ 1 V is applied to obtain the results for scaling the oxide thickness and device threshold voltage.

In a VLSI circuit, the selection of the device threshold voltage depends on the performance, and the multi-threshold voltage for a device can be chosen. The device with a high threshold voltage has high on-resistance due to low over-drive voltage $V_{\rm gs}$ -$V_{\rm th}$ and vice-versa. Figure 2(a) summarizes the effects of $V_{\rm th}$ scaling on the energy consumption of adiabatic and conventional CMOS inverter gates at 90 nm technology. In the device threshold voltage $V_{\rm th}$ range from 250 to 450 mV, the resistance portion of the intrinsic time constant $\tau_{\rm adia}$ (Eq. (9)) of the adiabatic gate increases, and this results in increased energy consumption $E_{\rm adia}$ (Eq. (10)). It can be observed that in the $V_{\rm th}$ range of 250 to 450 mV, the respective variation in adiabatic energy consumption $E_{\rm adia}$ is from 0.75 to 1.81 fJ, which is wider than the respective variation in conventional CMOS energy $E_{\rm conv}$ from 5.46 to 5.80 fJ. Towards the device threshold voltage scaling, the energy performance of adiabatic logic is more sensitive than the energy performance of conventional CMOS logic, and this trend should be taken into account when designing an adiabatic logic-based ultra-low application.

The supply voltage scaling trends for both the adiabatic and conventional CMOS inverter gates are shown in Fig. 2(b). We applied the supply voltage range from 0.7 to 1.4 V at an operating frequency equal to 250 MHz and load capacitance $C_{\rm L}$ $=$ 10 fF, and observed that the small variation in adiabatic energy consumption from 1.05 to1.2 fJ is observed. On the other hand, the conventional CMOS gates show a large variation from 2.2 to 11.7 fJ. This leads to the assumption that adiabatic logic is more robust against supply voltage variation, and in ultra-low applications the adiabatic logic allows aggressive voltage scaling. It can also be observed that at a supply voltage equal to 0.9 V ($\sim$3$V_{\rm th})$, the adiabatic logic consumes minimum energy, defined as the optimized supply voltage. Thus, the proposed model fits the simulation results under the scaling of device threshold voltage and supply voltage.

Finally, the energy performances are studied against the scaling of device gate oxide thickness $t_{\rm ox}$. Figure 2(c) presents the results of energy loss versus $t_{\rm ox}$ at a frequency of 250 MHz, a load capacitance $C_{\rm L}$ $=$ 10 fF, and a supply voltage of 1 V. With increasing $t_{\rm ox}$, the intrinsic time constant $\tau _{\rm adia}$ of an adiabatic gate (Eq. (9)) decreases, and therefore the energy consumption of an adiabatic gate $E_{\rm adia}$ (Eq. (10)) is increased. It can also be observed that for a variation in $t_{\rm ox}$, the respective variation in $E_{\rm adia}$ is wider than the respective variation in $E_{\rm conv}$ because in the deep-submicron VLSI design an increase in $t_{\rm ox}$ increases the device area and the threshold voltage and vice-versa^[13]. However, the energy consumption $E_{\rm adia}$ (Eq. (10)) of an adiabatic gate decreases with decreasing device threshold voltage and gate oxide thickness $t_{\rm ox}$, respectively. Therefore, a reduction in $V_{\rm th}$ at thin oxide $t_{\rm ox}$ would improve the energy performance of adiabatic logic, but in the case of conventional CMOS, a trade-off between $V_{\rm th}$ and $t_{\rm ox}$ is essential for improving the energy performance. Thus, the analysis of energy performance against $t_{\rm ox}$ scaling has allowed us to apply adiabatic switching in ultra-low-power applications at the nanoscale.

We also observed the scaling trends at the 65 nm CMOS technology node. Figures 3(a), 3(b) and 3(c) show the energy performance against the scaling of the $V_{\rm th}$, supply voltage and gate oxide thickness $t_{\rm ox}$, respectively. With the scaling of the device threshold voltage as shown in Fig. 3(a), the model expression follows the simulation results. As well as in the scaling of supply voltage and gate oxide thickness as shown in Figs. 3(b) and 3(c) respectively, the model tracks the simulation trends. Thus, the proposed model helps to discover how an adiabatic gate would respond toward the device threshold voltage, supply voltage and gate oxide thickness scaling.

Our motivation behind this work is to present a straightforward procedure for examining the scaling trends in adiabatic logic. The leakage power was not incorporated to derive a simple analytical model for investigating the scaling trends in adiabatic logic gates, hence minor validation error is observed in the results.

4. Conclusions

In this paper we have proposed an analytical model to estimate the energy performance of an adiabatic logic gate. To explore the importance of adiabatic logic at the nanoscale, the energy performance against the scaling of various device/design parameters has been analyzed and discussed. Extensive comparative analysis has been carried out at 90 nm and 65 nm CMOS technology nodes, and we attempted to prove that adiabatic switching is a straightforward low-power circuit technique at nanoscale CMOS technology. The validation results have proved that the proposed model is suitable for designing robust ultra-low-power adiabatic logic circuits.