1. Introduction

The Atacama large millimeter array (ALMA) vastly increases the ability to observe astronomical sources at millimeter and sub-millimeter wavelengths. As a key component, the ALMA front end system is the first element in a complex chain of signal receiving, conversion, processing, and recording. In addition, the front end is designed to receive signals from ten different frequency bands^[1]. Figure 1 displays a low-cost block diagram of the ALMA Front End system including two wideband LNAs, a wideband mixer and a wideband IF amplifier. The signals will be detected and received by the antenna array, then delivered to the ultra-low noise circuit implemented by HEMT devices on GaAs substrate. The intermediate frequency of the wideband mixer covers a wide frequency band of 4-12 GHz. The system has a demanding requirement in terms of sensitivity over the desired frequency range. Consequently, the noise figure, bandwidth, and gain play significant roles in the specifications of the wideband IF amplifier. The frequency response of the wideband IF amplifier is specified to cover 4-12 GHz. This paper presents a high-gain wideband low-noise IF amplifier aimed for band 1 (31.3-45 GHz) of the ALMA radio telescopes.

A considerable amount of research has been done on the ALMA Front End system in previous work. Furthermore, a low noise IF amplifier across 4-12 GHz has been achieved using InP HEMT devices combined with the cryogenic technique^[2]. By contrast, using CMOS devices is a more challenging task due to the inherent defects in the process. There are several wideband amplifier designs which show a good bandwidth performance^{[3, 4]}, however, the gain and bandwidth cannot meet the requirements of the system. Perhaps cascading several chips together is a solution, which needs an additional matching network. It is better to transfer the signal in terms of power in discrete component circuits, but in terms of voltage in integrated circuits. Therefore, the matching network between two circuits is redundant in integrated circuits. There are also some other disadvantages, such as area, loss, and gain flatness. Allowing for the application of the system, the output terminal will be directly connected to a spectrum analyzer to observe the spectrum of the received signals. In prior studies, a high power output buffer, incorporated with an external bias-T, was proposed to drive 50 $\Omega $ load and obtain the performance of the core circuit^[4]. Actually, it means the core circuit cannot drive 50 $\Omega $ load. In order to drive the 50 $\Omega $ load directly, the output stage of the proposed IF amplifier employs peaking techniques, which enhance the gain and bandwidth simultaneously. The proposed high-gain wideband low-noise IF amplifier, matched to 50 $\Omega $, has achieved not only an acceptable noise figure, but also a flat gain over the frequency range of 4-12 GHz.

This paper analyzes the key issues: topology, input matching, noise figure, and gain. After stating the details of the circuit design, this paper describes the proposed high-gain wideband low-noise IF amplifier. The measured results are then shown and compared to the simulated results.

2. Principle of the proposed IF amplifier design

To obtain a wideband high gain, three cascading stages are utilized. Furthermore, allowing for the cost of the chip, there are no matching networks between the stages, which means the signal is transferred in terms of voltage. Figure 2(a) shows the block diagram of the proposed IF amplifier. The frequency response of every stage is different from the others, as shown in Fig. 2(b). Following this design strategy, we discuss some principles of the proposed IF amplifier and provide some guidelines.

2.1 Topologies for low noise design

Apart from amplification of the signal, the amplifier must be stable enough to prevent self-oscillation with minimum added noise. There are various classical low noise circuit topologies that combine adequate input matching, as shown in Fig. 3. Due to the inherent input impedance $g^{-1}_{\rm m}$, the common gate topology shown in Fig. 3(a) has good input matching performance over a wide frequency band. Unfortunately, in order to achieve 50 $\Omega $ input matching, it yields a lower NF bound of 1 $+$ $\mathit{\Gamma}/\alpha$ > 2.2 dB^[3]. Furthermore, the DC operating point of the common gate transistor is inflexible, which results in a barrier to the gain and noise figure optimization. The noise cancellation was proposed to lower the noise figure of the common gate topology^{[5, 6]}. However, the validated range of this technique is very limited due to the time delay of the noise cancellation path. Up to now, the reported works have not exceeded 5 GHz. As a comparison, common source topology with the degeneration inductor shown in Fig. 3(b) is much more competitive in terms of gain and noise performance^[7]. However, the input impedance strongly depends on frequency and is equal to 50 $\Omega $ only at the resonant point of the tank of $L_{\rm s}$, $L_{\rm g}$, and $C_{\rm gs}$ in a low-frequency design. (Due to the influence of the Miller effect caused by the intrinsic gate-drain capacitance $C_{\rm ds}$, the input impedance can achieve 50 $\Omega $ across a wide frequency band in millimeter wave integrated circuits design.) It is still not suitable for our desired frequency of 4-12 GHz. As will be shown, the common source topology with negative feedback shown in Fig. 3(c) adopted in this design supplies good solutions to the wideband input matching, gain, and acceptable noise figure.

2.2 Wideband input matching

As well known, the performance of the input stage has a great impact on the performance of the overall circuit. So some equations and tradeoffs relevant to input matching and gain will be presented.

Figure 4 shows the schematic and small signal equivalent circuit of the active source follower shunt feedback amplifier. $C_{\rm L}$ represents the input capacitance of the next stage. The input impedance can be derived as:

$ $$\begin{equation} \begin{split} Z_1={}& (1/g_{\rm m3}+R_2) \bigg[1+g_{\rm m1}[(R_1+sL_2)/\!/ \\& g_{\rm m2}r_{\rm ds2}r_{\rm ds1}/\!/\frac{1}{sC_1}] +sC_{\rm gs1}\bigg(R_2+\frac{1}{g_{\rm m3}}\bigg)\bigg]^{-1}. \end{split} \end{equation}$$ $

(1)

Equation (1) shows the formula of the input impedance $Z_1$, which has allowed for various parasitic factors, such as the intrinsic gate-source capacitance $C_{\rm gs}$ and the channel resistance $r_{\rm ds}$.

$ $$\begin{equation} Z_1 \approx \frac{1/g_{\rm m3}+R_2} {1+g_{\rm m1}\left(R_1+sL_2\right)}. \end{equation}$$ $

(2)

Equation (2) supplies a guideline for the input matching of the low frequency preliminary design. Obviously, there is only one optimal frequency point matching to 50 $\Omega$. The value of $g_{\rm m1}$ and $R_{1}$ are based on the specifications of the gain and noise figure. At the expense of power, a larger $g_{\rm m1}$ can not only increase the gain, but also optimize the noise figure. The additional $R_{2}$ can suppress the second-order distortion of M3, which deteriorates IIP3 of the active source follower shunt feedback amplifier^[3]. Therefore, a larger $R_{2}$ will be preferable if linearity is a key indicator.

In the active shunt feedback circuit, it is a tradeoff among gain, noise figure, and input matching. Furthermore, the frequency response of input impedance and gain are inversely proportional to the loop gain while the noise figure is in opposition. The loop gain is dominated by and proportional to $g_{\rm m3}$. Therefore, $g_{\rm m3}$ is a critical parameter for optimization. A small value of $g_{\rm m3}$ is preferable to achieve high gain and a low noise figure. Unfortunately, $g_{\rm m3}$ has a great influence on the input matching and a smaller value of $g_{\rm m3}$ will worsen the input matching. Our focus should be how to release or appease this contradiction. Figure 5 gives the schematic of the proposed active shunt feedback input stage with the additional input series inductor $L_{1}$ and the series peaking inductor $L_{5}$. $L_{1}$ and $L_{5}$ supply a good solution to the tradeoff without additional power consumption. Ignoring some subordinate parasitic factors, Equation (3) gives the input impedance of the input stage shown in Fig. 5.

$ $$\begin{equation} \label{eq1} \begin{split} Z_{\rm in} {}& =sL_1 +Z_1 \\[2mm]& =sL_1 + \frac{1/g_{\rm m3} +R_2}{1+g_{\rm m1} (R_1 +sL_2 )+sC_{\rm gs1} (R_{2} +1/g_{\rm m3})}. \\ \end{split} \end{equation}$$ $

(3)

To gain insight into how the input series inductor $L_{1}$ increases the matching bandwidth, the $\mathit{\Gamma}_{\rm in}$ of the circuit can be derived as:

$ $$\begin{equation} \label{eq2} \mathit{\Gamma} _{\rm in} =\left| \frac{Z_{\rm in} -Z_0}{Z_{\rm in} +Z_0} \right|, \end{equation}$$ $

(4)

where $Z_{0}$ is the reference impedance of 50 $\Omega$. Let $\mathit{\Gamma}_{\rm in}$ $=$ 0, then $Z_{\rm in}$ $=$ $Z_{0}$, and the equation can be derived as:

$ $$\begin{align*} \label{eq3} &\underbrace {s^2 \left( {L_1 \left[{g_{\rm m1} L_2 +C_{\rm gs1} \left(R_{2} +\frac{1}{g_{\rm m3} }\right)} \right]} \right)}_{\mbox{quadratic term introduced by} \, L_1} \\[2mm] &+s \left[{L_1 +g_{\rm m1} R_1 L_1-g_{\rm m1} Z_0 L_2-Z_0 C_{\rm gs1} \left(R_2 +\frac{1}{g_{\rm m3} }\right)} \right] \\[2mm] \;\;\;&+\frac{1}{g_{\rm m3} }+R_2 -Z_0 -g_{\rm m1} Z_0 R_1=0. \\ \end{align*}$$ $

(5)

Apparently, Equation (5) is a quadric equation with one unknown $s$, which has two solutions $s_{1}$, $s_{2}$. It means that a new zero is introduced by $L_{1}$. By means of adjusting the value of $L_{1}$, $s_{1}$ and $s_{2}$ can be separated from each other. As a result, the matching bandwidth is extended and enhanced. Meanwhile, $L_{1}$ and $C_{\rm gs1}$ build a series resonant tank, which also extends the bandwidth of gain. A small gain-peaking inductor $L_5$ with low quality factor, placed in the gate terminal of M2, can also enhance the gain of high frequency^[13]. It results in an increase of the loop gain and a decrease of $Z_{\rm in}$, and then optimizes the input impedance of the high frequency range. Figure 6 presents the simulated $S_{11}$ with and without $L_{1}$ and $L_{5}$. Caused by the non-ideal DC block $C_{\rm c}$, $S_{11}$ is above $-10$ dB at a low frequency range.

2.3 Noise optimization

Allowing for the area and complication of the design, we have not designed the matching network between the input stage and the intermediate stage. As is well known, the noise factor $F$ of the overall circuit depends on the input stage, which can suppress the intermediate stage noise.

Actually, every device in Fig. 5 contributes to the noise factor $F$ of the input stage to some degree, but as confirmed by analysis and simulation of the input stage, the dominant noise source is the channel thermal noise of M1, given by Eq. (6).

$ $$\begin{equation} \overline{i_{\rm n, \, d}^2}=4kT\frac{\mathit{\Gamma}}{\alpha}g_{\rm m1}\Delta f, \end{equation}$$ $

(6)

where $k$ is the Boltzmann constant, $T$ is the absolute temperature, $\Delta f$ is the noise bandwidth, $\mathit{\Gamma}$ is the thermal excess noise factor, and $\alpha$ is the ratio of the trans-conductance $g_{\rm m}$ and the output conductance $g_{\rm d0}$ at $V_{\rm DS}$ $=$ 0 V. The output noise voltage, caused by the channel thermal noise of M1, is given as follows:

$ $$\begin{equation} \label{eq5} \overline {v_{\rm n, \, o}^2} =\frac{\overline {i_{\rm n, \, d}^2}\left| {sL_2 +R_{\rm 1} } \right|^2} {\left| {1+g_{\rm m1} (sL_2 +R_{\rm 1} )\dfrac{g_{\rm m3} (sL_1 \, +\, R_{\rm s} )}{1 \, +\, g_{\rm m3} (sL_{\rm 1}\, +\, R_{\rm s}\, + \, R_2 )}} \right|^2}. \end{equation}$$ $

(7)

From Eq. (7), we can observe the merit of the input series inductor $L_{1}$, which increases the denominator. The simulation shown in Fig. 7(a) verifies it. When the value of $L_{1}$ increases, the denominator goes up and towards a limitation of a fixed value. However, the thermal noise of the parasitic resistance, which will induce thermal noise, goes up together with $L_{1}$, so the inductor $L_{1}$ has an optimum value. As shown in Fig. 7(b), the NF decreases by 10% with an optimal value of $L_{1}$.

In Eq. (7), note how the output noise voltage depends on the gain, which is approximately proportional to $g_{\rm m1}$. Theoretically, the noise can be arbitrarily lowered by optimizing $g_{\rm m1}$. A larger $g_{\rm m1}$ not only reduces the 1/$f$ noise that is a barrier to the noise factor of the low frequency range, but also suppresses the noise of the intermediate stage. On the other hand, a larger $g_{\rm m1}$ means a larger $WL$, which will increase the parasitic capacitance, such as $C_{\rm gs}$ and $C_{\rm ds}$. This contradiction limits the value of $g_{\rm m1}$ to some degree. Another dominant term of NF is $g_{\rm m3}$, which directly controls the loop gain. Figure 8 shows the variations of the simulated gain and NF versus $g_{\rm m3}$. On the condition of the input matching, a lower value $g_{\rm m3}$ will be preferable.

2.4 Techniques for gain and bandwidth

The system has demanding requirements on the IF amplifier gain and bandwidth. Therefore, much focus will be placed on the analysis of gain and bandwidth. As shown in Fig. 2(b), with the input stage and the intermediate stage, the frequency response almost covers the low frequency range, so some techniques must be employed in the output stage to enhance the gain and bandwidth.

Figure 9 shows three types of common source topology with an identical transistor and load resistor. Additionally, to compare the effects of different techniques, the employed inductors are the same size in terms of width, space, and turns. The structure of $L_{\rm s1}$ and $L_{\rm s2}$ is symmetrical, and $L_{\rm c3}$ is a center-tapped symmetrical inductor.

Figure 9(a) shows the series peaking circuit, which is composed of a series peaking inductor $L_{\rm s1}$ and a common source amplifier. $Q_{\rm s\_tank}$ is the quality factor of the series resonant tank $L_{\rm s1}$-$C_{\rm gs}$.

$ $$\begin{equation} \label{eq6} Q_{{\rm s\_tank}} (\omega _{01} )=\frac{{\rm j}\omega _{01} L_{\rm s1} }{r_{\rm s1} }=\frac{1}{{\rm j}\omega _{01} C_{\rm gs} r_{\rm s1}}, \end{equation}$$ $

(8)

where the $\omega_{01}$ is the resonant frequency of the tank $L_{\rm s1}$-$C_{\rm gs}$.

$ $$\begin{equation} \label{eq7} \omega _{01} =\frac{1}{\sqrt {L_{\rm s1} C_{\rm gs}}}. \end{equation}$$ $

(9)

Equation (10) shows how $L_{\rm s1}$ changes the input voltage $v_{\rm gs}$ of the transistor. With inspection into the dominator of Eq. (10), $v_{\rm gs}$ will increase as $\omega$ increases when $\omega$ < $\omega_{01}$, however, $v_{\rm gs}$ will decrease as $\omega$ increases when $\omega$ $>$ $\omega_{01}$. It means $v_{\rm gs}$ has a peak value at $\omega$ $=$ $\omega_{01}$.

Equation (11) gives the detailed formula of the voltage gain $A_{\rm v, series}$($\omega$). From Eq. (12), we can see that the series resonant tank can significantly boost the voltage gain $Q_{\rm s\_tank}$ times at the resonant frequency $\omega_{01}$. Apparently, if a narrow-band high gain is desired, high $Q$ devices will be preferable on the condition of stability. For example, the resonant frequency of the tank $L_{\rm s1}$-$C_{\rm gs}$ is chosen to be 16 GHz here. Figure 10 shows the relationship between the gain and the reactance of the tank. As illustrated, the circuit achieves a peak value of 13 dB at its resonant frequency.

$ $$\begin{equation} \label{eq8} \begin{split} v_{\rm gs} {}& =\frac{\dfrac{1}{{\rm j}\omega C_{\rm gs} }}{r_{\rm s1} +{\rm j}\omega L_{\rm s1} +\dfrac{1}{{\rm j}\omega C_{\rm gs} }}v_{\rm i} \\[2mm]& =\frac{1}{1-\dfrac{\omega ^2}{\omega _{01}^2 }+{\rm j}\omega C_{\rm gs} r_{\rm s1} }v_{\rm i}, \\ \end{split} \end{equation}$$ $

(10)

$ $$\begin{equation} \label{eq9} \begin{split} A_{\rm v, series} (\omega ){}& =\frac{v_{\rm o} }{v_{\rm i} }=\frac{v_{\rm o} }{v_{\rm gs} } \frac{v_{\rm gs} }{v_{\rm i}} \\[2mm]& =-\frac{1}{1-\dfrac{\omega ^2}{\omega _{01}^2 }+{\rm j}\omega C_{\rm gs} r_{\rm s1} } g_{\rm m} \left(R_{\rm L} /\!/\frac{1}{{\rm j}\omega C_{\rm ds}}\right), \\ \end{split} \end{equation}$$ $

(11)

$ $$\begin{equation} \label{eq12} \begin{split} A_{\rm v, series}(\omega _{01} ) {}& =-\frac{1}{1-\dfrac{\omega ^2}{\omega _{01}^2 }+{\rm j}\omega _{01} C_{\rm gs} r_{\rm s1} }g_{\rm m} \left(R_{\rm L} /\!/\frac{1}{{\rm j}\omega C_{\rm ds} }\right) \\[2mm]& =-Q_{\rm s\_tank} (\omega _{01} ) g_{\rm m} \left(R_{\rm L} /\!/\frac{1}{{\rm j}\omega _{01} C_{\rm gs}}\right). \\ \end{split} \end{equation}$$ $

(12)

Figure 9(b) shows the shunt peaking circuit, which is composed of a shunt peaking inductor $L_{\rm s2}$ and a common source amplifier. We can do a simple transformation:

$ $$\begin{equation} \label{eq13} R_{\rm Lp} =\left[{1+Q_{_{\rm p\_tank} }^2 (\omega )} \right] R_{\rm L}, \end{equation}$$ $

(13)

$ L_{\rm s2p} =\left[{1+1/Q_{_{\rm p\_tank}}^2 (\omega )} \right] L_{\rm s2}, $

(14)

where $Q_{\rm p\_tank}(\omega)$ is the quality factor of the parallel resonant tank $L_{\rm s2}$-$C_{\rm ds}$.

$ Q_{\rm p\_tank} (\omega )=\frac{{\rm j}\omega L_{\rm s2} }{R_{\rm L}}. $

(15)

$\omega_{02}$ is the resonant frequency of the parallel tank $L_{\rm s2}$-$C_{\rm ds}$.

$ $$\begin{equation} \label{eq14} \omega _{02} =\frac{1}{\sqrt {L_{\rm s2p} C_{\rm ds}}}. \end{equation}$$ $

(16)

Theoretically, the parallel resonant tank can augment the gain $Q_{\rm p\_tank}^{2}(\omega_{02})$ times at its resonant frequency, as shown in Eq. (18). Since $R_{\rm L}$ will be transferred to $R_{\rm Lp}$ $\approx$ $Q_{\rm p\_tank}^{2}(\omega_{02})$$R_{\rm L}$.

$ $$\begin{equation} \label{eq15} A_{\rm v, shunt} (\omega )=\frac{v_{\rm o}}{v_{\rm i}}=-g_{\rm m} \left(R_{\rm Lp} /\!/{\rm j}\omega L_{\rm s2p} /\!/\frac{1}{{\rm j}\omega C_{\rm ds}}\right), \end{equation}$$ $

(17)

$ $$\begin{equation} \label{eq16} A_{\rm v, shunt, max} (\omega _{02} )=-Q_{_{\rm p\_tank}}^2 (\omega _{02} ) g_{\rm m} R_{\rm L}. \end{equation}$$ $

(18)

However, the resonant frequency of the parallel resonant tank extremely exceeds our desired frequency range for the sake of the small capacitance of the tank. Actually, in order to achieve a flat gain, the peaking factor $m$, defined in Eq. (19), is typically chosen to be 2.4^[8].

$ $$\begin{equation} \label{eq17} m=\frac{R_{\rm L}^2 C_{\rm ds}}{L_{\rm s2}}. \end{equation}$$ $

(19)

Figure 9(c) shows the common source amplifier with a center-tapped inductor $L_{\rm c3}$. Shown in Fig. 11(a), the center-tapped inductor $L_{\rm c3}$ consists of two coupling coils $L_{\rm e1}$ and $L_{\rm e2}$, furthermore, $L_{\rm e1}=L_{\rm e2}$. This is a typical case to extend the bandwidth with the expense of group delay, which is similar to the distributed designs. The frequency response of the voltage gain can be derived as

$ $$\begin{equation} \label{eq18} A_{\rm v, ct} (\omega )=-g_{\rm m} \frac{{\rm j}\omega (1+k)L_{\rm e1} +R_{\rm L}} {-\omega ^2 2(1+k)L_{\rm e1} C_{\rm ds} +{\rm j}\omega R_{\rm L} C_{\rm ds} +1}. \end{equation}$$ $

(20)

To demonstrate the effect of the center-tapped inductor and the coupling factor $k$, $L_{\rm e1}=L_{\rm e2}$ $=$ 500 pH are chosen for example. Figure 11(b) shows the simulated group delay versus frequency with different coupling factor $k$. The frequency response of the voltage gain also varies along with the coupling factor $k$, as shown in Fig. 11(c). Observing Fig. 12, this circuit has a better performance than the shunt peaking circuit. By adjusting the size and coupling factor of the center-tapped inductor, the bandwidth can be significantly improved in a wideband design. The center-tapped inductor not only enhances the gain and bandwidth, but also facilitates the layout design.

Figure 12 displays a comparison of the improvement of the series peaking inductor $L_{\rm s1}$, the shunt peaking inductor $L_{\rm s2}$ and the center-tapped inductor $L_{\rm c1}$. It can be concluded that gain and bandwidth can be significantly enhanced without any additional power consumption. Furthermore, the series peaking inductor $L_{\rm s1}$ and the center-tapped inductor $L_{\rm c1}$ can be employed simultaneously in the gate and drain terminal of the transistor.

3. Proposed IF amplifier circuit

The required high gain motivates the design of multistage cascading amplifiers. Not every single stage needs a high and flat gain over the full frequency range, otherwise much more area and power would be cost. Instead, the gain of every stage shows a peak value in different frequency ranges. Constructed by three stages of cascading amplifiers, Figure 13 shows the schematic of the proposed high gain wideband low noise IF amplifier in 90 nm CMOS technology.

An efficient and validated design depends not only on the active device models, but also on the parasitic extraction of the passive elements. In order to improve the agreement between simulation and measurement, more accurate EM simulations are necessary to facilitate high frequency designs. In our previous work, it was verified that the EM simulation with exact settings could be reliable in our designs. Figure 14 gives the verification of EM simulation using an HFSS full wave simulator. The inductor, simulated in Fig. 14, is a standard octagonal structure with 3-$\mu $m width and 3.5 turns using the top metal. All the inductors and critical interconnect lines in this design were simulated using HFSS.

3.1 Input stage

Obviously, the consideration and design of the input stage is a key to achieving a good input matching while keeping a low noise figure and high gain over the desired frequency range. Consequently, much attention should be paid to the input stage. Active shunt feedback, as discussed in Section 2, is a commonly used technique in wideband amplifier design, which demonstrates good performance of input matching in a wide frequency range^[4]. Both shunt peaking and active source follower shunt feedback techniques are adopted in the input stage of the proposed design. The peaking technique is beneficial for enhancing the gain and bandwidth, but it also decreases the stability factor of the design. We should carefully optimize our design on the condition of good stability.

$ $$\begin{equation} \label{eq19} \begin{split} A_{\rm vs, input} ={}& \frac{v_{\rm o}}{v_{\rm s}} =\left\{-g_{\rm m1} \left[(R_1 +sL_2 )/\!/\frac{1}{sC_{\rm L}}/\!/g_{\rm m2} r_{\rm ds2} r_{\rm ds1} \right]\right\} \\[2mm]& \times 1+ R_{\rm s} +sL_{\rm 1} +g_{\rm m1} R_{\rm s} [(R_1 +sL_2 )/\!/\frac{1}{sC_{\rm L}}/\!/ \\[2mm]& g_{\rm m2} r_{\rm ds2} r_{\rm ds1}] R_2 +\frac{1}{g_{\rm m3}}^{-1} \\[2mm] \approx & \left[-g_{\rm m1} (R_1 +sL_2 )\right] \\[2mm]& \times \left[1+\frac{R_{\rm s} +sL_{\rm 1} +g_{\rm m1} R_{\rm s} (R_1 +sL_2 )}{R_2 +\dfrac{1}{g_{\rm m3} }}\right]^{-1} \\[2mm] ={}& \left[-g_{\rm m1} (R_1 +sL_2)\right] \left[1+\frac{g_{\rm m3} }{1+g_{\rm m3} R_2 }sL_{1} \right. \\[2mm]& \left. +\frac{g_{\rm m3} }{1+g_{\rm m3} R_2 }R_{\rm s} g_{\rm m1} (R_1 +sL_2) \right]^{-1}, \\ \end{split} \end{equation}$$ $

(21)

where $R_{\rm s}$ $=$ 50 $\Omega$ is the resistance of the voltage source. Equation (21) gives a simplified voltage gain of the input stage from a 50 $\Omega$ voltage source. By consideration of the tradeoff among the gain, noise and input matching, $g_{\rm m3}$ $=$ 3.2 mS and $R_{2}$ $=$ 90.6 $\Omega$ was chosen to weaken the influence of the denominator. As a result, $g_{\rm m3}/(1+g_{\rm m3}R_{2})$ is almost equal to 2.48 mS, which is so small that we only need to optimize the value of $L_{1}$ on the basis of noise performance. Finally, $L_{1}$ $=$ 667 pH was chosen. With inspection of Eqs. (2) and (15), a resistor of $R_{1}$ $=$ 28 $\Omega$ and a shunt peaking inductor of $L_{2}$ $=$ 920 pH was chosen to extend the bandwidth and achieve a flat gain^[8]. TL$_{1}$ was implemented by a micro-strip line (MSL) using the top thick metal 9 of 3.4-$\mu $m as the signal path and the bottom thin metal 1 of 0.24-$\mu $m as the reference ground. With a small value of 260-pH, TL$_{1}$ resonates with $C_{\rm gs2}$ (the gate capacitance of transistor M2). This series resonant tank can extend the bandwidth, but also deteriorate the stability of the feedback loop^[13]. An rg of 26 $\Omega$ was added here to decrease the quality of the series resonant tank and enhance the stability.

3.2 Intermediate stage

As known, a simple common source amplifier with purely resistive load has a high gain, which is proportional to $g_{\rm m}R_{\rm L}$. However, as fabrication technology scales down, the channel resistance $r_{\rm ds}$ will decrease the gain of $g_{\rm m}$$R_{\rm L}$//$r_{\rm ds}$. For example, the $r_{\rm ds}$ of a transistor, with a size of $W$/$L$ $=$ 48 $\mu$m/90 nm, is only about 400 $\Omega$. The cascade amplifier has a large output resistance due to the common gate transistor, and it has a higher gain than a common source amplifier. The intermediate stage, composed of three cascode amplifiers and one common source amplifier, supplies a high gain at a low frequency range. The voltage gain can be easily derived as:

$ $$\begin{equation} \label{eq20} A_{\rm v, inter} =g_{\rm m4} g_{\rm m6} g_{\rm m8} g_{\rm m10} R_4 R_5 R_6 (R_7 /\!/r_{\rm ds10}). \end{equation}$$ $

(22)

To overcome DC drift and ensure the flexibility of the bias, the intermediate stage only utilizes capacitive coupling, together with one control voltage $V_2$. In the proposed IF amplifier, $R_{4}=R_{5}=R_{6}$ $=$ 120 $\Omega$ and $R_{7}$ $=$ 105 $\Omega$ are chosen.

3.3 Output stage

The output stage employs a series peaking inductor $L_{3}$ and a center-tapped inductor $L_{4}$ to enhance the high frequency gain and extend the bandwidth. We should give top priority to the stability factor when optimizing the gain and bandwidth. Figure 15 shows the schematic and small-signal equivalent circuit of the output stage. $R_{\rm load}$ is the 50 $\Omega$ load resistance standing for the terminal of the test instrument and $Z_{\rm d12}$ is the output impedance of M12, which is

$ $$\begin{equation} \label{eq21} Z_{\rm d12} \approx g_{\rm m12} \left(r_{\rm ds12} /\!/\frac{1}{sC_{\rm ds12}}\right)\left(r_{\rm ds11} /\!/\frac{1}{sC_{\rm ds11}}\right). \end{equation}$$ $

(23)

The voltage gain of the output stage can be derived as:

$ $$\begin{equation} \label{eq22} \begin{split} {}& A_{\rm v, output} = -\frac{1}{s^2L_{\rm s1} C_{\rm gs} +sC_{\rm gs} r_{\rm s1} +1} g_{\rm m} \\[4mm]& \times \frac{R_{\rm load} /\!/\left[{R_{\rm L} +sL_{\rm e1} (1+k)} \right]} {Z_{\rm d12} /\!/\left( {sL_{\rm e1} (1+k)+R_{\rm load} /\!/\left[{R_{\rm L} +sL_{\rm e1} (1+k)} \right]} \right)}. \\ \end{split} \end{equation}$$ $

(24)

From inspection of the circuit, it is easy to observe that there are two resonant tanks caused by the additional introduced series peaking inductor $L_{3}$ and center-tapped inductor $L_{4}$. The resonant frequency of the parallel resonant tank is chosen to extremely exceed our desired frequency range to allow for the output matching to 50 $\Omega$.

Finally, $L_{3}$ $=$ 1.2 nH and $L_{4}$ $=$ 1.3 nH are chosen, the coupling factor between the two coils of $L_{4}$ is close to 0.65. In order to ensure stability, $R_{8}$ is added to decrease the quality of the parallel resonant tank. Incorporating with $L_{4}$, $R_{8}$ offers good output matching with a value of 30 $\Omega $. The proposed amplifier can directly drive 50 $\Omega $ load without any additional high power output buffer.

Figure 16 shows the voltage gain contributed by every single stage. As can be seen from the curves, the voltage gain of every stage makes different contributions to the voltage gain of the proposed IF amplifier at different frequency ranges. The input stage has a peak value of 9 dB at 10 GHz. The intermediate stage supplies 30 dB at low frequency. The peak value of the output stage is 11.5 dB at 15 GHz. Consequently, the proposed IF amplifier, constructed by the three stages, achieves a flat gain over a wide frequency range.

4. Experimental results

The proposed high-gain wideband low-noise IF amplifier circuit was fabricated in TSMC 90-nm LP CMOS technology with 9 metal layers and an aluminum layer on top. To minimize the resistive loss, the top layer was utilized to realize the long interconnection lines as well as the inductors. Furthermore, the vital long signal lines have been simulated using an HFSS 3D EM-simulator. Figure 17 displays the chip micrograph of the proposed IF amplifier with a chip area of 0.7 $\times$ 0.76 mm$^{2}$ and an active area of 0.06 $\times$ 0.36 mm$^{2}$. The dc biases of the gate terminals are $V_1=V_2=V_3=$ 0.7 V. The DC power consumption was observed to be a little higher than the simulated value. The wideband IF amplifier drained 35 mA current at a supply voltage of 1.2 V and consumed 42 mW. As shown below, the measured experimental results are in good agreement with the simulation.

The $S$-parameters were measured using an Agilent E8363A power network analyzer, shown in Fig. 18. The proposed IF amplifier exhibits an excellent performance of gain fluctuation (30 $\pm$ 0.3 dB) across 4-12 GHz. Furthermore, the 3 dB bandwidth ranges from 1 to 16 GHz, which can easily satisfy many wideband applications. The output-to-input isolation indicated by $S_{12}$ is below $-48$ dB in the desired band of 4-12 GHz.

Figure 19 shows the measured noise figure together with the simulated result. The noise figure was measured using an Agilent E8975A noise analyzer. In addition, the noise figure was kept below 4.4 dB over the desired frequency range of 4-12 GHz, offering a minimum noise figure of 3.76 dB.

A two-tone test with 2 MHz separation was performed to obtain the IIP3. The signal generators Agilent E8257D and R&S SMP04 accounted for the generation of a two-frequency tone, respectively. The output signals were captured by an Agilent E4440A spectrum analyzer. The measured OIP3 is equal to 5.6 dBm at 6 GHz and 8 dBm at 10 GHz. Figure 20 shows the $P_{\rm in, \, 1 dB}$ and IIP3 curves over the frequency range of 4-16 GHz. The measured power gain and output power versus input power is shown in Fig. 21.

In order to compare with prior studies, the figure of merit (FOM) is introduced here. Since this design focuses on the performance of gain, bandwidth, and noise figure, the definition is given in Eq. (25). Table 1 gives a summary of the proposed IF amplifier and comparisons with prior studies.

$ $$\begin{equation} \label{eq23} {\rm FoM}=\frac{{\rm Gain}_{\rm avg} [{\rm linear}] \cdot{\rm BW}_{\rm 3dB} [{\rm GHz}]} {P_{\rm DC} {\rm [mW]} \cdot (F_{\rm min} -1)[{\rm linear}] \cdot {\rm Area}[{\rm mm}^2]}. \end{equation}$$ $

(25)

5. Conclusion

This work has presented the design of a high-gain wideband low-noise IF amplifier for the ALMA radio telescopes. The input stage employs active shunt feedback, which is a good solution to input matching to 50 $\Omega$. Both series peaking and shunt peaking techniques have been introduced to extend the bandwidth. Noise analysis and optimization has also been presented. The proposed wideband low noise IF amplifier circuit has achieved a good performance in terms of gain, gain fluctuation, noise figure, and input matching in a wide frequency range.

Acknowledgment: The authors are very grateful for support from the Institute of RF & OE ICs, Southeast University and Engineering Research Center of RF-ICs & RF-Systems, Ministry of Education. The authors also thank Zhang Li and Li Wei for help with layout tutoring and chip measurement.