Fig. 1.
The architecture of the differential-type SAR ADC.
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| Citation: |
Quanliang Li, Liyuan Liu, Ye Han, Zhongxiang Cao, Nanjian Wu. A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors[J]. Journal of Semiconductors, 2014, 35(10): 105008. doi: 10.1088/1674-4926/35/10/105008
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Q L Li, L Y Liu, Y Han, Z X Cao, N J Wu. A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors[J]. J. Semicond., 2014, 35(10): 105008. doi: 10.1088/1674-4926/35/10/105008.
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A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors
DOI: 10.1088/1674-4926/35/10/105008
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Abstract
This paper presents a 12-bit column-parallel successive approximation register analog-to-digital converter (SAR ADC) for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital-to-analog converter (CDAC) and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20×2020 μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-V supply and decreases linearly as the frame rate decreases. -
References
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