Processing math: 100%
J. Semicond. > 2014, Volume 35 > Issue 3 > 035006

SEMICONDUCTOR INTEGRATED CIRCUITS

A hearing aid on-chip system based on accuracy optimized front-and back-end blocks

Fanyang Li and Hao Jiang

+ Author Affiliations

 Corresponding author: Li Fanyang, Email:qingsheng11081@sina.com

DOI: 10.1088/1674-4926/35/3/035006

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Abstract: A hearing aid on-chip system based on accuracy optimized front-and back-end blocks is presented for enhancing the signal processing accuracy of the hearing aid. Compared with the conventional system, the accuracy optimized system is characterized by the dual feedback network and the gain compensation technique used in the front-and back-end blocks, respectively, so as to alleviate the nonlinearity distortion caused by the output swing. By using the technique, the accuracy of the whole hearing aid system can be significantly improved. The prototype chip has been designed with a 0.13 μm standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for driving a 16 Ω loudspeaker with a normalized output level of 300 mVp-p, the total harmonic distortion reached about -60 dB, achieving at least three times reduction compared to the previously reported works. In addition, the typical input referred noise is only about 5 μ Vrms.

Key words: front-endback-endpre-amplifierdriving amplifierhearing aid

For those patients with hearing impairment, a hearing aid is indispensable, since acoustic signals such as normal talking needs to be amplified and processed. Thus, in order to offer a certain improvement in sound quality for enhancing a patient's hearing ability, the accuracy of the hearing aid on-chip system's signal processing needs to be improved.

In the previous works, digital implementation[1] has achieved the highest accuracy. However, it requires high-precision AD/DA conversions and DSP, giving rise to an extra considerable area and cost. In a contrast, analog implementation[2-5] does not require AD/DA and DSP, saving the area of the chip and cost. So, as a result, a low cost hearing aid on-chip system usually utilizes the analog approach. Categorically, analog implementation is mainly divided into the pulse width modulation (PWM) technique with a class D driver[2, 3] and the continuous time (CT) technique with a class AB driver[4, 5]. The PWM technique can optimize the power efficiency by driving the class D driver with a digital signal. However, its accuracy is not satisfactory because of the carrier signal's nonlinearity[3]. With respect to the PWM technique, the CT technique[4, 5] can improve the accuracy with the class AB driver. However, as the open loop gain of the class AB driver changes or decreases seriously with the output swing increasing or the loudspeaker impedance decreasing, the nonlinearity distortion in such designs usually increases considerably. Moreover, the front-end feedback network also induces nonlinearity because of the requirement for automatic gain control (AGC)[6, 7].

To improve the accuracy of the system under a low supply voltage, this paper presents the accuracy optimized hearing aid system, which is characterized by the system internal gain and feedback compensation, so as to reduce the transferring error in the automatic gain control preamplifier and in the driver, respectively. The accuracy optimized system architecture with the gain and feedback technique is described in Section 2. The implementations corresponding to the compensation technique are discussed in Section 3. The measurement results are presented in Section 4. Conclusions are drawn in Section 5.

A conventional analog hearing aid system using the CT technique[5], as shown in Fig. 1, is constituted by the front end (the AGC preamplifier block) and the back end (the loudspeaker driver). The preamplifier usually adopts an MOS resistive circuit (MRC) as the feedback network to achieve the automatic gain control, while the driver usually utilizes a class AB amplifier to realize the whole system.

Figure  1.  The conventional hearing aid system.

Since both the preamplifier and the driver blocks are operational amplifiers with closed loops, for reducing the nonlinearity, the relationship of the preamplifier or the driver's transfer function with the open loop gain and the feedback coefficient should be expressed as follows:

T(Gopenloop,ffeedback)=Gopenloop1+ffeedbackGopenloop,

(1)

where Gopenloop is the open loop gain of the preamplifier or the driver, and the ffeedback is the feedback coefficient. Accordingly, the nonlinearity transfer characteristics should be formulated as follows:

Nnonlinearity=T(Gopenloop-gain,ffeedback)Gopenloop_gainΔG+T(G openloop-gain,ffeedback)ffeedbackΔffeedback,

(2)

where ΔG openloop-gain and Δffeedback are the variation of the open loop gain and feedback coefficient, respectively. According to the above analysis on the nonlinearity, the mathematic transferring model of the conventional system is given, as shown in Fig. 2.

Figure  2.  The transferring mathematic model of the conventional hearing aid system.

In Fig. 2, G openloop-preamp and G openloop-driver present the ideal open loop gains of the preamplifier and the driver; while α and β present the ideal feedback coefficient of the preamplifier and the driver, respectively. Moreover, considering the nonlinearity of the feedback network and the open loop gain of the amplifier in the system, the coefficients N1-N4 need to be introduced to denote the nonlinearity factors. In the system, N1 is caused by the deviation of the preamplifier's open loop gain; while N2 is induced by the degradation of the driver's open loop gain. N3 is generated by the deviation of the preamplifier's feedback coefficient; while N4 is produced by the deviation of the driver's feedback coefficient. Combined with Eq. (2), N1-N4 may be estimated by the following equations:

{N1=ΔG openloop-preamp1+αG openloop-preamp,N2=ΔG openloop-driver1+βG openloop-driver,N3=Δαα,N4=Δββ,

(3)

where ΔG openloop-preamp and ΔG openloop-driver are the open loop gain deviation of the preamplifier and driver; Δα and Δβ are the feedback coefficient deviation of the preamplifier and the driver, respectively. Therefore, according to the model shown in Fig. 2, the transfer function of the conventional system can be expressed as follows:

F(Vout/Vin)=(1α+Δαα+ΔG openloop-preamp1+αG openloop-preamp)×(1β+Δββ+ΔG openloop-driver1+βG openloop-driver).

(4)

Since the feedback network of the driver is the resistor and capacitor array, the Δβ can be ignored. Moreover, the ΔG openloop-preamp can also be negligible because of the preamplifier's considerable loading impedance. So the transfer function of the system can be deduced as follows:

F(Vout/Vin)=(1α+Δαα)(1β+ΔG openloop-driver1+βG openloop-driver).

(5)

As the value of the feedback network (such as the MRC[7]) in the preamplifier block becomes variable with the changeable drain-source voltage Vds, which is related to the output swing of the block, as shown in Fig. 3(a), the feedback coefficient deviation Δα increases. Moreover, for the large open loop gain of the driving amplifier, a folded cascaded amplifier[5] is usually adopted to drive the class AB output stage, as illustrated in Fig. 3(b). As the large current sources or sinks with the output swing greatly increase or the loudspeaker impedance decreases, the cascaded transistors (M1, M2 or M3, M4) of the amplifier are induced into the linear region because of the fixable shifted voltage. Therefore, the gain of the folded cascaded amplifier G openloop-driver will decrease seriously. For the above reasons, according to Eq. (5), the transferring accuracy of the system could be degraded.

Figure  3.  (a) The topology of the MRC block. (b) The topology of the driving amplifier.

To overcome these challenges, the architecture of the proposed accuracy enhanced on-chip system is shown in Fig. 4. Actually, the compensation technique is illustrated in the front and back end: in the front-end preamplifier, unlike only MRC feedback in the conventional system, there exist dual feedback networks[8]: the passive resistor array and the MRC. The passive resistor array is enabled to enhance the sound quality in the low input sound level, which is needed by the patients; while the MRC feedback network control by the automatic control unit[9-11] is then utilized to compress the high input sound level, which is unwanted by the patients. Compared with the nonlinearity factor of the MRC in a conventional system varied by the output swing, the nonlinearity factor of the resistor array in the proposed system can be ignored. In terms of the back-end driver, unlike conventional drivers using the CT technique, when the output swing of the driver is greatly increased, the audio signal is compensated and amplified with the gain compensation block, and then the amplified signal drives the output stage.

Figure  4.  The proposed accuracy enhanced system with the compensation technique.

Assuming the ideal open loop gains and the feedback coefficients of the preamplifier and the driver in the conventional and proposed systems are equal, the transfer function of the proposed system can be expressed as follows:

F(Vout/Vin)=1α(1β+ΔGcompensated1+βG openloop-driver),

(6)

where ΔGcompensated is the gain variation with the gain compensation technique. With the gain compensation block, the ΔGcompensated would be also greatly reduced compared with the ΔG openloop-driver  in the conventional system. Therefore, the accuracy of the proposed system's output signal in the low sound level should be enhanced.

Details of the dual feedback network compensation technique implemented in the preamplifier[8, 12, 13] are shown in Figs. 5(a) and 5(b). Specifically, the preamplifier is divided into two phases: the amplification phase and the gain control phase, as shown in Fig. 5(a). To determine which phase the preamplifier is operating in, the envelope detector[14, 15] shown in Fig. 5(b) senses the preamplifier's positive output envelope voltage V PD-P and compares it with the VTH (the patient's selective knee voltage of the system). Simultaneously, the detector outputs the negative output envelope voltage V PD-N, which is inversely proportional to the V PD-P[8].

Figure  5.  (a) The feedback network in the amplification phase. (b) The feedback network in the gain control phase.

When the V PD-P is less than VTH, the system is in the amplification phase. The topology of the resistor array shown in Fig. 5(a) is enabled to enhance the accuracy of the amplification. The gain Aamp should equalize the gain Acontrol in the gain control phase at VTH in order to achieve smooth gain transition at the boundary of the two phases[8]. The equation can be expressed as follows:

Rfeedback1nRin=W1L2n(1+V PD-NVLHVddVC)W2nL1(1V PD-NVLHVddVC)|V PD-N=VTH,

(7)

where the Rin and Rfeedback1n denote the values of the input and feedback passive resistor array respectively. W1n and L1n correspond to the MOS transistor sizes in the MRC1-n; and VC is the common mode voltage of the gain control voltages V1 and V2; VLH is the reference voltage of the system, as shown in Fig. 5(b). Moreover, in the amplification phase, with the variable feedback coefficients (Rfeedback1n), the patients can choose their preferred level of system gain[16].

When V PD-P is larger than VTH, the system is in the gain control phase, and the MRC array feedback network shown in Fig. 5(b) is enabled while the resistor array is turned off. Meanwhile, the gain control unit shown in Fig. 5(b) begins to control the MRC array. The gain in this phase should be expressed as follows:

Againcontrol_phase=W1L2n(1+V PD-NVLHVddVC)W2nL1(1V PD-NVLHVddVC).

(8)

While V PD-P is increasing, V PD-N reduces. With V PD-N decreasing infinitely near to VLH, the gain compression ratio should be expressed as follows:

Compression_Ratio=W1L2nW2nL1.

(9)

According to the equation above, to realize the selection of the gain compression ratio for the patients, MRC2-n are designed with different W/L in the system.

The topology of the driving amplifier with the gain compensation technique is shown in Fig. 6. The amplifier is constituted by a folded cascade OTA, a clamp circuit and an output stage. The folded cascade OTA consists of two micro OTAs[17] (OTA1 and OTA2) and the cascaded output stage, as shown in Fig. 6, which are used to increase the open-loop gain. The clamp circuit plays an important role in the gain compensation of the driving amplifier, while the output stage is utilized to source and sink the large current of the loudspeaker. The resistor R and the capacitor C split the poles of the folded cascade OTA and the output stage's output impedance.

Figure  6.  The topology of the proposed driving amplifier with the gain compensation technique.

In the case of the low swing voltage outputted by the driver, the clamp circuit plays no role on the signal processing, because of the folded cascade OTA's low output voltage range. Accordingly, the corresponding adaptable shifted voltage Vshifted between the gate voltages of the transistors M5 and M6 should be expressed as follows:

Vshifted=VDD|Vgs_M5|Vgs_M6,

(10)

where Vgs_M5 and Vgs_M6 is the gate to source voltage of M5 and M6, respectively. Since the M5 and M6's gate voltages are not clamped, the value of Vgs_M6 is almost complementary to the absolute value of Vgs_M5. Therefore, the adaptable shifted voltage is approximately at the constant value.

Thus, the gain of the folded cascade OTA could be obtained by converting the OTA1 and OTA2's adding current into the output voltage with the cascaded output stage (constituted by M7, M8, M11 and M9, M10, M12). Therefore, the open loop gain of the driver should be as the following equation:

Glowswing=(gm_OTA1+gm_OTA2)RcascadeGoutputstage,

(11)

where the gm_OTA1 and gm_OTA2 are OTA1 and OTA2's trans-conductances, respectively. Rcascade is the output impedance of the folded cascade OTA and the Goutputstage is the gain of the driver output stage.

With the high output swing, the clamp circuit takes effect. The clamp circuit ensures that OTA1 and OTA2's output cascade transistors (M7, M8 and M9, M10) are in the saturated region.

The detailed implementation of the clamp circuit is shown in Fig. 6. To ensure the range of the OTA's output voltage, the current source Iref is designed to be at a constant value. The sizes of transistors M1, M2 and M3 are designed to be equal; and with no load the transistors M1 and M2 operate in the linear region. Specifically, when the loudspeaker sources the large current from the output stage, transistor M1 goes into the deeply linear region because of Iref. When the transistor M2 enters into the saturated region, the current of transistor M3 mirrors the current of transistor M2. So the current of transistor M4 in the clamp circuit should be expressed as follows:

IQ4=Iref.

(12)

Therefore, the adaptable shifted voltage between the gate voltage of transistors M5 and M6 would be reduced with a large sourcing current, and the gate to source voltage Vgs of the transistor M6 would be clamped at:

V gs_M6-Clamp=2Iref(W/L)4+VTHN,

(13)

where (W/L)4 is the size ratio of transistor M4. When the loudspeaker sinks the large current into the output stage, transistor M2 goes into the deeply linear region because of Iref. Thus the drain to source voltage Vds of the transistor M2 can be ignored and the current of transistor M1 remains to be Iref:

IQ1=Iref.

(14)

So the shifted voltage between the gate voltage of transistors M5 and M6 would be reduced, and the gate to source voltage Vgs of the transistor M5 would be clamped at:

|V gs_M5-Clamp|=2Iref(W/L)1+|VTHP|,

(15)

where (W/L)1 is the size ratio of transistor M1. Thus, the corresponding adaptable shifted voltage Vshifted with the large sourcing or sinking current should be expressed as follows:

{Source: Vshifted=VDD2Iref(W/L)4VTHN|Vgs_M5|,Sink: Vshifted=VDD2Iref(W/L)1|VTHP|Vgs_M6.

(16)

Therefore, when the output swing's amplitude becomes large, the shifted voltage between the gate voltages of transistors M5 and M6 is achieved to be adaptable. And with the clamp circuit, the range of the OTA's output voltages is obtained as follows:

Vrange=VDD(2Iref(W/L)4+2Iref(W/L)1+VTHN+|VTHP|),

(17)

where VTHN or VTHP is the transistor threshold voltage of the PMOS or NMOS. So if the overdrive voltages of output transistors M7, M8 and M10, M12 satisfy the following equation:

{2Iref(W/L)1+|VTHP||Voverdrive_M7+Voverdrive_M8|,2Iref(W/L)4+VTHNVoverdrive_M10+Voverdrive_M12,

(18)

the output transistors of the folded cascade OTA can be guaranteed to be operating in the saturated region, regardless of the output swing's amplitude, as shown in Fig. 7.

Figure  7.  The illustration of the folded cascaded OTA output voltage's range.

When the folded cascade OTA's transistors are operating in the saturating region, the gain compensation technique can be implemented. When the current sources the large current from the output stage, the effective driving amplifier is equivalent to the left block shown in Fig. 8(a). The block is constituted of the OTA1 and OTA2, the cascaded stage (consisting of the M7, M8 and M9, M10) and M6's current limited output stage. The output impedance of the cascaded stage should be compensated to be a large value, because of the saturated operating region, in which the cascaded transistors (M7, M8 and M9, M10) are operating. The gain of the driving amplifier in this case should be expressed as follows:

Ghighswing_currentsource=(gm_OTA1+gm_OTA2)Rcascade1Goutputstage1,

(19)
Figure  8.  The topology of the effective driving amplifier. (a) The large current sourcing. (b) The large current sinking.

where the Rcascade1 is the output impedance of M7, M8 and M9, M10's cascaded stage; the Goutputstage1 is the gain of M6's current limited output stage.

Likewise, when the current sinks the large current into the output stage, the effective driving amplifier is equivalent to the right block shown in Fig. 8(b). The block is constituted of OTA1, 2, the cascaded stage (consisting of the M7, M11 and M10, M12) and M5's current limited output stage. The gain of the driving amplifier should be as follows:

Ghighswing_currentsink=(gm_OTA1+gm_OTA2)Rcascade2Goutputstage2,

(20)

where Rcascade2 is the output impedance of M7, M11 and M10, M12's cascaded stage; the Goutputstage2 is the gain of M5's current limited output stage. So when the large current sinks into or sources from the output stage, the driver with the compensated gain can be realized.

The proposed design was fabricated on a 0.13 μm standard CMOS process and the chip occupies 2.25 mm2 silicon area excluding pads, as shown in Fig. 9. It was tested at a power supply voltage of 1 V, with a sinusoid input signal at a typical audio frequency of 1 kHz. The experimental results are summarized as follows.

Figure  9.  The microscope photograph of the analog hearing aid system on chip.

As shown in Fig. 10(a), the measured noise average density[18] at the system output is about 1.60 μV/Hz. This translates into a system input referred noise of 5 μVrms in the audio frequency bandwidth (100-10 kHz), where the corresponding system gain in the amplification phase is normalized to be 30 dB. With the loudspeaker impedance of 16 Ω to be driven and the gain of 30 dB, the measured HD3 and THD about 64 dB and 60 dB with the normalized output voltage 300 mV p-p is shown in Fig. 10(b). Moreover, the THD is also measured versus the received power of the 16 Ω loudspeaker, as shown in Fig. 11. In Fig. 11, the THD of the proposed system does not degrade significantly with the output power increased.

Figure  10.  (a) The output noise of the hearing aid system. (b) The THD of the system with 300 mVp-p.
Figure  11.  The THD under various output power (16 Ω loudspeaker).

With the gain of 30 dB in amplification phase and the selective knee voltage VTH 45 mV, the measured system output characteristics versus the different compression ratio (1: 2, 1: 3, 1: 4) is shown in Fig. 12. With the compression ratio 1: 4, the system gain reduction with the increase of the input voltage is illustrated on Fig. 13. With the input voltage 4 mVpp increasing to 40 mVpp, the peak to peak amplitude of the output voltage is limited to the 250 mVpp and the gain 30 dB of the system is reduced to 15 dB.

Figure  12.  The output characteristics of the hearing aid system.
Figure  13.  The gain reduction with the increase of the input voltage (16 Ω loudspeaker).

The system performances compared with other hearing aid systems are summarized in Table 1. In this work, under a supply voltage of 1 V, the THD performance is reduced to 60 dB with the normalized output swing of 300 mVpp despite the fact that the loudspeaker impedance is reduced to 16 Ω. Moreover, this work is a complete system, with the compression ratio range, the input referred noise and the area getting an advantage over or comparable with other approaches. With the impedance of the loudspeaker decreasing, the patient's hearing sound volume would be larger. But since the output stage's power dissipation with the load is inversely proportional to the loading impedance[5], more power is consumed by the system. Therefore, only the following parameters of the power (excluding the output stage with the loudspeaker), THD, area, and the input referred noise are included for the simplicity of evaluation. A form of the FOM can be defined as follows:

FOM=103THD×Noise×Power no-outputstage×Area.

(21)
Table  1.  Performance comparison.
DownLoad: CSV  | Show Table

From Table 1, we can see that the FOM arising from this work is improved significantly in comparison with other works.

This paper has demonstrated a hearing aid on-chip system that uses the gain and feedback compensation technique. According to our results, with the dual feedback network preamplifier and the gain compensated driver, the accuracy of the system with the ultra-low impedance of the loudspeaker is improved significantly compared with the other works. The noise and the power excluding the output stage's power dissipation are comparable with the other approaches. Moreover, the nonlinearity distortion performance does not degrade significantly with the increasing received power of the ultra-low impedance loudspeaker. Hence, the accuracy optimized system on chip has been achieved for the hearing aid.



[1]
Gata D G, Sjursen W, Hochschild J R, et al. A 1.1 V 270μ A mixed-signal hearing aid chip. IEEE J Solid-State Circuits, 2002, 37(12):1670 doi: 10.1109/JSSC.2002.804328
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Silva-Martinez J, Solis-Bustos S, Schellenberg M. A CMOS hearing aid device. Analog Integrated Circuit and Signal Processing, 1999, SC-21(2):163 http://dl.acm.org/citation.cfm?id=339109
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Serra-Graells F, Gomez L, Huertas J L. A true-l-V 300-μ W CMOS-sub threshold log-domain hearing-aid-on-chip. IEEE J Solid-State Circuits, 2004, 39(8):1271 doi: 10.1109/JSSC.2004.831469
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Azzolini C, Boni A. A 1-V CMOS audio amplifier for low cost hearing aids. Proc 15th IEEE Int Conf on Electronics, Circuit and Systems, St. Julien's, 2008:562 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=4674915
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Fig. 1.  The conventional hearing aid system.

Fig. 2.  The transferring mathematic model of the conventional hearing aid system.

Fig. 3.  (a) The topology of the MRC block. (b) The topology of the driving amplifier.

Fig. 4.  The proposed accuracy enhanced system with the compensation technique.

Fig. 5.  (a) The feedback network in the amplification phase. (b) The feedback network in the gain control phase.

Fig. 6.  The topology of the proposed driving amplifier with the gain compensation technique.

Fig. 7.  The illustration of the folded cascaded OTA output voltage's range.

Fig. 8.  The topology of the effective driving amplifier. (a) The large current sourcing. (b) The large current sinking.

Fig. 9.  The microscope photograph of the analog hearing aid system on chip.

Fig. 10.  (a) The output noise of the hearing aid system. (b) The THD of the system with 300 mVp-p.

Fig. 11.  The THD under various output power (16 Ω loudspeaker).

Fig. 12.  The output characteristics of the hearing aid system.

Fig. 13.  The gain reduction with the increase of the input voltage (16 Ω loudspeaker).

Table 1.   Performance comparison.

[1]
Gata D G, Sjursen W, Hochschild J R, et al. A 1.1 V 270μ A mixed-signal hearing aid chip. IEEE J Solid-State Circuits, 2002, 37(12):1670 doi: 10.1109/JSSC.2002.804328
[2]
Silva-Martinez J, Solis-Bustos S, Schellenberg M. A CMOS hearing aid device. Analog Integrated Circuit and Signal Processing, 1999, SC-21(2):163 http://dl.acm.org/citation.cfm?id=339109
[3]
Serra-Graells F, Gomez L, Huertas J L. A true-l-V 300-μ W CMOS-sub threshold log-domain hearing-aid-on-chip. IEEE J Solid-State Circuits, 2004, 39(8):1271 doi: 10.1109/JSSC.2004.831469
[4]
Serra-Graells F, Huertas J L. Low voltage CMOS-sub threshold log amplification and AGC. IEE Proc Circuits Devices Syst, 2005, 152(1):61 doi: 10.1049/ip-cds:20041003
[5]
Azzolini C, Boni A. A 1-V CMOS audio amplifier for low cost hearing aids. Proc 15th IEEE Int Conf on Electronics, Circuit and Systems, St. Julien's, 2008:562 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=4674915
[6]
Hauptmann J, Dielacher F, Steiner R. A low-noise amplifier with automatic gain control and anti-clipping control in CMOS technology. IEEE J Solid-State Circuits, 1992, SC-27(7):974 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=142591
[7]
Kim S, Lee J Y, Song S J, et al. An energy-efficient analog front-end circuit for a sub-1 V digital hearing aid. IEEE J Solid-State Circuits, 2006, SC-41(4):876 http://ieeexplore.ieee.org/document/1610632/
[8]
Li F, Yang H, Liu F, et al. Dual-mode gain control for a 1 V CMOS hearing aid device with enhanced accuracy and energy-efficiency. Journal of Analog Integrated Circuit and Signal Processing, 2012, 72(2):495 doi: 10.1007/s10470-012-9844-5
[9]
IEC. Hearing aids with automatic gain control circuits. Technical Report 118-2, 1983 http://infostore.saiglobal.com/store/Details.aspx?productID=661208
[10]
Zhak S M, Baker M W. A low-power wide dynamic range envelop detector. IEEE J Solid-State Circuits, 2003, SC-38(10):1750 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=1233793
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    Received: 28 August 2013 Revised: 29 September 2013 Online: Published: 01 March 2014

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      Fanyang Li, Hao Jiang. A hearing aid on-chip system based on accuracy optimized front-and back-end blocks[J]. Journal of Semiconductors, 2014, 35(3): 035006. doi: 10.1088/1674-4926/35/3/035006 ****F Y Li, H Jiang. A hearing aid on-chip system based on accuracy optimized front-and back-end blocks[J]. J. Semicond., 2014, 35(3): 035006. doi: 10.1088/1674-4926/35/3/035006.
      Citation:
      Fanyang Li, Hao Jiang. A hearing aid on-chip system based on accuracy optimized front-and back-end blocks[J]. Journal of Semiconductors, 2014, 35(3): 035006. doi: 10.1088/1674-4926/35/3/035006 ****
      F Y Li, H Jiang. A hearing aid on-chip system based on accuracy optimized front-and back-end blocks[J]. J. Semicond., 2014, 35(3): 035006. doi: 10.1088/1674-4926/35/3/035006.

      A hearing aid on-chip system based on accuracy optimized front-and back-end blocks

      DOI: 10.1088/1674-4926/35/3/035006
      Funds:

      the National High Technology Research and Development Program of China 2008AA010701

      Project supported by the National High Technology Research and Development Program of China (No. 2008AA010701)

      More Information
      • Corresponding author: Li Fanyang, Email:qingsheng11081@sina.com
      • Received Date: 2013-08-28
      • Revised Date: 2013-09-29
      • Published Date: 2014-03-01

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