Fig. 1.
Block diagram of the $N$ -bit cyclic ADC with 1.5 bits/cycle architecture.
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| Citation: |
Kaiming Nie, Suying Yao, Jiangtao Xu, Zhaorui Jiang. A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor[J]. Journal of Semiconductors, 2014, 35(3): 035005. doi: 10.1088/1674-4926/35/3/035005
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K M Nie, S Y Yao, J T Xu, Z R Jiang. A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor[J]. J. Semicond., 2014, 35(3): 035005. doi: 10.1088/1674-4926/35/3/035005.
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A 10-bit ratio-independent cyclic ADC with offset canceling for a CMOS image sensor
DOI: 10.1088/1674-4926/35/3/035005
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Abstract
A 10-bit ratio-independent switch-capacitor (SC) cyclic analog-to-digital converter (ADC) with offset canceling for a CMOS image sensor is presented. The proposed ADC completes an N-bit conversion in 1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversion characteristic of the proposed cyclic ADC is inherently insensitive both to capacitor ratio and to amplifier offset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18-μm one-poly four-metal CMOS technology. The measured results indicate that the ADC has a signal-to-noise and distortion ratio (SNDR) of 53.6 dB and a DNL of +0.12/-0.14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 μ W with a 1.8 V supply, and its area is 0.03×0.8 mm2. -
References
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