Performance analysis of silicon nanowire transistors considering effective oxide thickness of high-<i>k</i> gate dielectric

S. Theodore Chandra; N. B. Balamurugan

doi:10.1088/1674-4926/35/4/044001

J. Semicond. > 2014, Volume 35 > Issue 4 > 044001

SEMICONDUCTOR DEVICES

Performance analysis of silicon nanowire transistors considering effective oxide thickness of high-k gate dielectric

S. Theodore Chandra and N. B. Balamurugan

+ Author Affiliations

Corresponding author: S. Theodore Chandra, Email: theodore@tce.edu

DOI: 10.1088/1674-4926/35/4/044001

Abstract: We have analyzed the effective oxide thickness (EOT) of the dielectric material for which we have optimum performance and the output characteristics of the silicon nanowire transistors by replacing the traditional SiO₂ gate insulator with a material that has a much higher dielectric constant (high-k) gate, materials like Si₃N₄, Al₂O₃, Y₂O₃ and HfO₂. We have also analyzed the channel conductance, the effect of a change in thickness, the average velocity of the charge carrier and the conductance efficiency in order to study the performance of silicon nanowire transistors in the nanometer region. The analysis was performed using the Fettoy, a numerical simulator for ballistic nanowire transistors using a simple top of the barrier (Natori) approach, which is composed of several matlab scripts. Our results show that hafnium oxide (HfO₂) gate insulator material provides good thermal stability, a high recrystallization temperature and better interface qualities when compared with other gate insulator materials; also the effective oxide thickness of HfO₂ is found to be 0.4 nm.

Key words: high-k dielectric, hafnium oxide, silicon nanowire transistor, effective oxide thickness

References

[1]	Moore G E. Progress in digital integrated electronics. Electron Devices Meeting, 1975 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=1478174
[2]	Plummer J D, Griffin P B. Material and process limits in silicon VLSI technology. IEEE Proceedings, 2001:240 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=915373
[3]	Kang C Y, Choi R, Lee B H, et al. Reliability characteristics of La-doped high-k/metal gate nMOSFETs. J Semicond Technol Sci, 2009, 9(3):166 doi: 10.5573/JSTS.2009.9.3.166
[4]	Bohr M T, Chau R S, Ghani T, et al. The high-k solution. IEEE Spectrum, 2007, 44:29 doi: 10.1109/MSPEC.2007.4337663
[5]	Rao V R, Mohapatra N R. Device and circuit performance issues with deeply scaled high-k MOS transistors. J Semicond Technol Sci, 2004, 4(1):52 http://repository.ias.ac.in/80931/
[6]	Chu P K. Advances in solid state circuits technologies. Croatia:INTECH, 2010
[7]	Chau R, Datta S, Doczy M, et al. High-k/metal-gate stack and its MOSFET characteristics. IEEE Trans Electron Devices Lett, 2004, 25:408 doi: 10.1109/LED.2004.828570
[8]	Rahman A, Guo J, Datta S, et al. Theory of ballistic nanotransistors. IEEE Trans Electron Devices, 2003, 50:1853 doi: 10.1109/TED.2003.815366
[9]	Natori K. Ballistic metal-oxide-semiconductor field effect transistor. J Appl Phys, 1994, 76(8):4879 doi: 10.1063/1.357263
[10]	https://nanohub.org , 2013
[11]	Rahman A, Wang J, Guo J, et al. FETToy. 2009, https://nanohub.org/resources/fettoy
[12]	Fodor J K, Guo J. Introduction to FETToy. 2007. https://nanohub.org/resources/2844

Fig. 1. Schematic device structure of nanowire transistor.

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Fig. 2. Plot of drain current versus gate voltage for different dielectric materials (a) in linear scale and (b) in log scale.

DownLoad: Full-Size Img PowerPoint

Fig. 3. Plot of drain current versus gate voltage by varying the oxide thickness using HfO$_{2}$ as the dielectric material.

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Fig. 4. Plot of drain current versus gate voltage for $V_{\rm DS}$ of 1 V and 25 mV (a) using SiO$_{2}$ as the gate dielectric and (b) using HfO$_{2}$ as the gate dielectric.

DownLoad: Full-Size Img PowerPoint

Fig. 5. Plot of average velocity versus gate voltage by varying the gate dielectric material.

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Table 1. List of dielectric constant for different gate materials.

[1]	Moore G E. Progress in digital integrated electronics. Electron Devices Meeting, 1975 http://ieeexplore.ieee.org/xpl/abstractKeywords.jsp?reload=true&arnumber=1478174
[2]	Plummer J D, Griffin P B. Material and process limits in silicon VLSI technology. IEEE Proceedings, 2001:240 http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=915373
[3]	Kang C Y, Choi R, Lee B H, et al. Reliability characteristics of La-doped high-k/metal gate nMOSFETs. J Semicond Technol Sci, 2009, 9(3):166 doi: 10.5573/JSTS.2009.9.3.166
[4]	Bohr M T, Chau R S, Ghani T, et al. The high-k solution. IEEE Spectrum, 2007, 44:29 doi: 10.1109/MSPEC.2007.4337663
[5]	Rao V R, Mohapatra N R. Device and circuit performance issues with deeply scaled high-k MOS transistors. J Semicond Technol Sci, 2004, 4(1):52 http://repository.ias.ac.in/80931/
[6]	Chu P K. Advances in solid state circuits technologies. Croatia:INTECH, 2010
[7]	Chau R, Datta S, Doczy M, et al. High-k/metal-gate stack and its MOSFET characteristics. IEEE Trans Electron Devices Lett, 2004, 25:408 doi: 10.1109/LED.2004.828570
[8]	Rahman A, Guo J, Datta S, et al. Theory of ballistic nanotransistors. IEEE Trans Electron Devices, 2003, 50:1853 doi: 10.1109/TED.2003.815366
[9]	Natori K. Ballistic metal-oxide-semiconductor field effect transistor. J Appl Phys, 1994, 76(8):4879 doi: 10.1063/1.357263
[10]	https://nanohub.org , 2013
[11]	Rahman A, Wang J, Guo J, et al. FETToy. 2009, https://nanohub.org/resources/fettoy
[12]	Fodor J K, Guo J. Introduction to FETToy. 2007. https://nanohub.org/resources/2844

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Received: 08 October 2013 Revised: 30 October 2013 Online: Published: 01 April 2014

We have analyzed the effective oxide thickness (EOT) of the dielectric material for which we have optimum performance and the output characteristics of the silicon nanowire transistors by replacing the traditional SiO₂ gate insulator with a material that has a much higher dielectric constant (high-k) gate, materials like Si₃N₄, Al₂O₃, Y₂O₃ and HfO₂. We have also analyzed the channel conductance, the effect of a change in thickness, the average velocity of the charge carrier and the conductance efficiency in order to study the performance of silicon nanowire transistors in the nanometer region. The analysis was performed using the Fettoy, a numerical simulator for ballistic nanowire transistors using a simple top of the barrier (Natori) approach, which is composed of several matlab scripts. Our results show that hafnium oxide (HfO₂) gate insulator material provides good thermal stability, a high recrystallization temperature and better interface qualities when compared with other gate insulator materials; also the effective oxide thickness of HfO₂ is found to be 0.4 nm.

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