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J. Semicond. > 2014, Volume 35 > Issue 4 > 045010

SEMICONDUCTOR INTEGRATED CIRCUITS

A method for timing constrained redundant via insertion

Junping Wang1, 2, , Dan Xu1 and Yongbang Su2

+ Author Affiliations

 Corresponding author: Wang Junping, Email:jpwang@mail.xidian.edu.cn

DOI: 10.1088/1674-4926/35/4/045010

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Abstract: Redundant via (RV) insertion is a useful mechanism to enhance via reliability. However, when extra vias are inserted into the design, the circuit timing might be changed. Therefore, how to insert RV under the timing constraints is the main challenge. In this paper, we introduce a new model to compute the distance between a RV and the corresponding single via, put forward a new RV type, which is called the long length via (LLV), and then present an improved RV insertion method considering the timing constraints. This computing model can certify that the timing, which is obtained after inserting a RV, is not greater than the original timing. Meanwhile, the new RV type LLV can increase the possibility of RV insertion; this method provides a global perspective for the RV insertion. Considering the timing constraints, the total redundant via insertion rate is 85.38% in the MIS-based method, while our proposed method can obtain a high insertion rate 88.79% for the tested circuits.

Key words: redundant viatiming constraintsintegrated circuit

As the technology node enters into the nanometer era, the concept of yield-driven design becomes increasingly important for modern chip designs[1-7]. Any via failure in an interconnect caused by electromigration, thermal stress and random defects has become one of the most important difficulties[8-11]. Without violating any design for manufacturability (DFM) design rules and to improve via reliability, a redundant via (RV) provides an alternative path. Therefore, redundant via insertion has become one of the well-known and highly recommended methods to improve the via reliability.

In general, redundant via insertion is performed in a post-routing stage[12-26]. The first work of the RV insertion in the detailed maze routing was proposed by Xu et al.[14]. Lee et al.[15] formulated the RV insertion problem as a maximum independent set (MIS) problem in the post-routing stage; however, the MIS-based method is an NP-complete problem, it would take much execution time to complete it. For a higher insertion rate, Chen et al.[16] formulated the RV insertion problem as one or more bipartite matching problems, but the optimality can be guaranteed only when the design is grid-based and involves up to three routing layers. The other method was proposed by Chang et al.[17], who introduced a novel via pattern, rectangle via (REV) for dead vias, which has the same function as the traditional double via (DV) and has lower resistance than that of a single via (SV), but they have not presented a new insertion method. The now available methods are proposed based on the assumption that the timing delay of each net does not alter before and after RV insertion. However, inserting the RV may change the original circuit design. So the yield and circuit function might be altered during the RV insertion[14-20]. Luo et al.[25] considered the timing issue, but the insertion algorithm cannot guarantee whether the circuit timing is degraded or not after the insertion. Pan et al.[26] and Yan et al.[27] developed an insertion approach considering the timing constraints. However, the objects were only confined to DV rather than the varying length RV.

In this paper, considering the timing constraints, a new RV insertion method is proposed to solve the RV insertion task from the global perspective. Moreover, we deduce the process to compute the distance between a RV and the corresponding single via, we also put forward an improved redundant via type, which is defined as long length via (LLV). Then, a new weighted model to determine the insertion order is proposed. According to the technology requirements, the DV structure has priority over REV's and LLV's, while the REV structure has priority over LLV's. The experimental results show that our proposed insertion approach not only can effectively insert the redundant via, but also properly control the circuit timing delays to guarantee the demands in circuit function and circuit yield.

In this section, the problem of the timing delays for RV insertion is demonstrated. Then we introduce the process to compute varying lengths for RV insertion under the timing constraints. We conclude this part with the RV insertion method.

Redundant via insertion is a highly recommended method to improve via reliability. However, the RV occupies more routing resources than a normal SV does for grid-based routing methods; redundant via insertion might change the circuit timing delay and then alter the circuit function. It is necessary to guarantee the timing delay between nets during redundant via insertion for DFM requirement.

Figure 1 shows the layout patterns and required resources of SV, DV, REV and LLV. Here, it is assumed that the width of the via and minimum spacing between two nets are λ and that the metal enclosure of the via is 0.5λ. We assume that x is the length between a single via and the corresponding RV. If the x is equal to zero, the RV is REV. If the x is equal to λ, the RV is DV. LLV is the varying length RV which the length x is more than λ to meet technological requirements. When x is more than λ, we choose the minimum length.

Figure  1.  The occupied area of routing patterns. (a) SV. (b) DV. (c) REV. (d) LLV.

According to the connection between nets and the single via, the structures of redundant vias can be categarized into two different shapes. The L-shape, (this structure looks like the letter 'L') in which a single via only connects two net segments. The T-shape, (this structure looks like the letter 'T') in which a single via connects more than two net segments.

The methods to calculate the timing delay for different RV types are different; the particular models for different RV types are shown in Ref. [26]. Considering the limit of the size of paper, we introduce the detailed computing processes in the following typical model, which can effectively give expression to the calculation process. In order to accurately calculate the Elmore timing delay, we transform the redundant via to the equivalent acyclic RC circuits. Then, we can obtain the redundant via structure under the timing constraints and its insertion site by analyzing the change of timing delay. The redundant via insertion should meet the timing delay conditions (τL/Ton/off τL/To). The τL/To is the original circuit timing delay and the τL/T is the circuit timing delay after inserted RV. In the timing delay formula, x is the only variable. It is can be found that adjusting x can satisfy the timing constraints. Suppose that the unit length resistance and the unit length capacitor are equal in adjacent metal (r1=r2=rw, c1=c2=cw). After that, we can work out the range of x, as shown in the following section.

As shown in Fig. 2, we can easily find that the via provides the connection of nets between two adjacent metal layers and this template is on-track type Ⅰ in an L-shape RV. Assume that τLo is known, the timing delay of this template is τLon1 by estimate using the Elmore timing delay model.

τLon1=Rso[c1(L1x)+(2cvLv+c1x+c2x)+c2L2+Csi]+r1(L1x)[c1(L1x)2+(2cvLv+c1x+c2x)+c2L2+Csi]+(r1x+rvLv)(r2x+rvLv)(r1x+rvLv)+(r2x+rvLv)×(cvLv+c1x2+c2x2+c2Lv+Csi)+r2L2(c2L22+csi).

(1)
Figure  2.  On-track type Ⅰ in L-shape RV.

The redundant via insertion should meet the timing conditions. The timing constraint is

τLon1τLo.

(2)

By plugging τLon1 into Eq. (2), then Equation (2) can be simplified as

x21+(3cvLv2cwrvLv2rwL1+L22Rsorw+Csi2cw)x1+(rvLvL22rwcvLvL1cwcvLvRsorwcw+rvLvCsi2rwcw)0.

(3)

Moreover, by calculating the quadratic Eq. (3), the x1 can be obtained.

x1(,B1B214C12][B1+B214C12,+),

(4)

where B1, C1 are related to the other parameters as follows.

B1=3cvLv2cwrvLv2rwL1+L22Rsorw+Csi2cw,

(5)

C1=rvLvL22rwcvLvL1cwcvLvRsorwcw+rvLvCsi2rwcw.

(6)

According to this model above, we can work out the other templates' x. Then, the range of x in the varying length redundant via, so as to insert the redundant via, can be obtained.

Based on the definition above, we can assign a weight w to candidate RV to determine the sequence of candidate RV. further, we can use x to decide the RV type and to express the length between the RV and the corresponding SV. In a post-routing design, the candidate RV set V(w,x) is constructed for inserting RV under the timing constraints. For each candidate RV, a value of weight w is assigned according to several properties between the corresponding SV and the other related RV candidates; x is the varying length to the corresponding SV worked out by the method noted above. When x is equal to 0, this candidate RV's type is REV. When x is equal to λ, this candidate RV's type is DV. The others candidate RV's type is LLV. The weight w is

w=η(αA+βB+γC),

(7)

where a, β and γ are user-specified constants. A is the number of the feasible RV candidates of the responding SV. B is the number of conflict among the other feasible RV candidates. The value of C is set to 0 if it is an on-track RV candidate. Otherwise, C is assigned to be 1.

According to the technology requirements, the DV structure has priority over REV's and LLV's, and the REV structure has priority over LLV's. When this RV has a DV structure to the corresponding SV, the value of η is 1. When the RV has a REV structure to the corresponding SV, the value of η is 2. When the RV has a LLV structure to the corresponding SV, the value of η is 3.

Based on the weighted model above, we propose a modified timing constraint RV insertion method. The insertion steps are shown as follows.

Step 1. Analyze the timing delay and find the x for each RV that is satisfied with the design rule. Construct the corresponding V(w,x) and calculate the w by Eq. (7).

Step 2. Choose a via vi,j which w is minimum in the set V(w,x) and w is not equal to infinity, put this via into the set Vsol (the initial value of Vsol is empty).

Step 3. Insert this RVi,j to replace the former structure, and delete the vi,j and the other vias related to vi,j from set V(w,x).

Step 4. Recalculate the w for each via in set V(w,x), if the V(w,x) is not empty or all the rest of w is equal to infinity, go back to step 2, or else finish.

After finishing the steps above, we have completed the inserting process to all single vias that can be inserted by RV under critical area and timing constraints.

This method has been implemented in the C++ programming language on a dual core 2.1-GHz PC with 4-GB memory. Four tested circuits have been applied to test the via insertion in the proposed method. The four circuits are adder, subtracter, multipliers and divider, respectively, all of which are 4-bit. As shown in Table 1, the circuit scales are gradually increasing. The four layouts, which correspond to the circuits above, have been changed into the multi-layer plane figure and are of a Caltech intermediate form (CIF) file format. We can obtain the position of via and nets in the layout; the vias layer and corresponding two metal layers can be extracted by analyzing the plane figure. Then, we can implement the following experiments. Since on-track RVs costs less routing resource and have better electrical properties than off-track RV's, we choose α=3, β=1 and γ=2 in our experiments. Here we assume that a single via failure rate is 0.00001 and that the failure probability of the wire is 0.000001[28].

Table  1.  Test circuit information.
DownLoad: CSV  | Show Table

We have classified experiments into three groups to illustrate the effectiveness of our method. The circuits' major and relevant information is listed in Table 1. In those tables, for each test circuit, "test circuit" represents the circuit name, and "single vias" indicates the number of single vias. "R. L." gives the number of routing layers. "Nets" shows the number of nets. "W. L. (mm)" shows the length of interlinked wires. "Ins. RV" shows the number of the new inserted vias. "R (%)" is the insertion rate that is equal to divide "Ins. RV" by "single vias", which range from 0 to 100%. "Yield (%)" is the circuit's yield, and the yield is generally calculated by a negative binomial model or Poisson model[29], the computing process in this paper is similar to Ref. [28]. As shown in Table 2, this experimental group shows the results by using the insertion method under no constraint. The insertion rate is 92.45%, the wire length increases only in the range of 2.3646% to 5.5821%, while the yield increases in the range of 0.00053 to 0.0214 mm.

Table  2.  RV insertion under no constraint with our method.
DownLoad: CSV  | Show Table

As shown in Table 3, this experimental group shows the results by using the insertion method under the timing constraints. The insertion rate is 88.79%. In Table 4, we have completed the RV insertion with the proposed method in Ref. [26]. The total insertion rate is 85.38%, and the incremental yield is 0.049% to 1.979% compared to the original circuit. In Tables 2 and 3, it is easily found that the insertion rate and the yield have a lower rate, but it ensures the delay characteristic to satisfy the demand in circuit design. From Tables 3 and 4, we can see that our method can get a higher insertion rate and yield than in Ref. [26]. In Ref. [26], the insertion problem is solved by a timing-driven minimum weighted matching algorithm, but the objects were only confined to DV rather than the varying length RV and the insertion problem might fall into local optimum. It can be found that the presentation of varying length RV leads to increase the RV insertion rate compared to the existing methods, and the insertion method completes the RV insertion task from the global perspective, so it can increase the possibility of RV insertion and the timing-driven method can guarantee the circuit timing and function. Therefore, our method can improve the redundant via insertion rate and assure the circuit function simultaneously.

Table  3.  RV insertion under timing constraint with our method.
DownLoad: CSV  | Show Table
Table  4.  RV insertion under timing constraint in Ref. [26].
DownLoad: CSV  | Show Table

Redundant via (RV) insertion is highly recommended for improving the via reliability. At the same time, inserting a RV adjacent to a single via can alter circuit timing delay. In this paper, we consider the post-routing RV insertion problem under the timing constraints. Besides, we introduce a model to compute varying length and present an improved RV insertion method from the global perspective. The experimental results show that the proposed method can effectively insert the RV and, compared to the no constraints driven method, the proposed constraints driven method has a good control of the circuit timing delays to guarantee the demands in circuit function and circuit yield. Therefore, this paper has great significance in improving the via reliability. This model could be further applied to the other layout optimization process.



[1]
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[2]
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[3]
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[4]
Wang Junping, Hao Yue. Yield modeling of rectangular defect outline. Chinese Journal of Semiconductors, 2005, 26(8):1514 http://www.oalib.com/paper/1518454
[5]
Liang Tao, Jia Xinzhang. An empirical formula for yield estimation from singly truncated performance data of qualified semiconductor devices. Journal of Semiconductors, 2012, 33(12):125008 doi: 10.1088/1674-4926/33/12/125008
[6]
Yang Yintang, Leng Peng, Dong Gang, et al. RLC interconnect delay with temperature distribution effects. Journal of Semiconductors, 2008, 29(9):1843 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=07112202&flag=1
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Li X, Wang J M, Tang W, et al. Stochastic analysis of interconnect delay in the presence of process variations. Journal of Semiconductors, 2008, 29(2):304 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=07082201&flag=1
[8]
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[9]
Ducotey G, Couvrat A, Audran V. In-line methodology for defectivity analysis form dark field wafer inspection to defect root cause analysis using FIB cut. Advanced Semiconductor Manufacturing Conference, 2008 http://ieeexplore.ieee.org/document/4529041/?reload=true&arnumber=4529041&punumber%3D4519622
[10]
Izuka T, IkedaM, Asada K. Timing-aware cell layout de-compaction for yield optimization by critical area minimization. IEEE Trans VLSI Syst, 2007, 15(6):716 doi: 10.1109/TVLSI.2007.898754
[11]
Wang J P, Hao Y. Critical area computation for real defects and arbitary conductor shapes. Acta Electronica Sinica, 2006, 34(4):1974 http://cpb.iphy.ac.cn/EN/Y2006/V15/I7/1621
[12]
Beanato G, Giovannini P, Cevrero A. Design and testing strategies for modular 3-D-multiprocessor systems using die-level through silicon via technology. IEEE J Emerging and Selected Topics in Circuits and Systems, 2012, 2(2):295 doi: 10.1109/JETCAS.2012.2193837
[13]
Ting F C, Tsang C K, Shih H Y. Enhanced redundant via insertion with multi-via mechanisms. IEEE Computer Society Annual Symposium on VLSI, 2011 http://ieeexplore.ieee.org/document/5992483/
[14]
Xu G, Huang L D, Pan D Z. Redundant-via enhanced maze routing for yield improvement. Proceedings of the ASP-DAC, 2005 http://dl.acm.org/citation.cfm?id=1120927
[15]
Lee K Y, Koh C K, Wang T C. Fast and optimal redundant via insertion. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(12):2194 http://ieeexplore.ieee.org/document/4670066/
[16]
Chen H Y, Chiang M F, Chang Y W. Full-chip routing considering double-via insertion. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2010, 27(5):844 http://dl.acm.org/citation.cfm?id=2301984
[17]
Chang T F, Kan T C, Yang S H. Enhanced redundant via insertion with multi-via mechanisms. The 14th IEEE Computer Society Annual Symposium on VLSI, 2011 http://ieeexplore.ieee.org/document/5992483/
[18]
Kan T C K, Yang S H, Chang T F. Design of a practical nanometer-scale redundant via-aware standard cell library for improved redundant via1 insertion rate. IEEE Trans VLSI Syst, 2013, 21(1):142 doi: 10.1109/TVLSI.2011.2176968
[19]
Yao H L, Cai Y, Zhou Q. Multilevel routing with redundant via insertion. IEEE Trans Circuits Syst, 2006, 53(10):1148 doi: 10.1109/TCSII.2006.881822
[20]
Allan G A. Targeted layout modifications for semiconductor yield/reliability enhancement. IEEE Trans Semicond Manufacturing, 2004, 17(4):573 doi: 10.1109/TSM.2004.835727
[21]
Hao Ran, Wang Huijuan, Yu Daquan, et al. High-speed through-silicon via filling method using Cu-cored solder balls. Journal of Semiconductors, 2012, 33(8):086002 doi: 10.1088/1674-4926/33/8/086002
[22]
Haltmeier M. Stable signal reconstruction via minimization in redundant, non-tight frames. IEEE Trans Signal Processing, 2013, 61(2):420 doi: 10.1109/TSP.2012.2222396
[23]
Shen J W, Chiang M F, Chen S. Redundant via allocation for layer partition-based redundant via insertion. IEEE 8th International Conference on ASIC, 2009 http://ieeexplore.ieee.org/document/5351310/
[24]
Liang J, Chen S, Yoshimura T. Redundant via insertion based on conflict removal. ICSICT, 2010 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5667425
[25]
Luo F, Jia Y, Dai W M. Yield-preferred via insertion based on novel geotopological technology. Asia and South Pacific Conference on Design Automation, 2006 http://dl.acm.org/citation.cfm?id=1118469
[26]
Pan C W, Lee Y M. Redundant via insertion under timing constraints. The 12th International Symposium on Quality Electronic Design, 2011 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5770794
[27]
Yan J T T, Chen Z W, Chiang B Y. Timing-constrained yield-driven redundant via insertion. APPCCAS, 2008 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4746363
[28]
Yan J T, Chiang B Y, Chen Z W. Yield-driven redundant via insertion based on probalilistic via-insertion analysis. International Conference on Electronics, Circuits and Systems, 2006 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4263506
[29]
Hao Y. Theory and methods of integrated circuits manufacturing dynamics. Beijing:Beijing Educational Press, 1995:132
Fig. 1.  The occupied area of routing patterns. (a) SV. (b) DV. (c) REV. (d) LLV.

Fig. 2.  On-track type Ⅰ in L-shape RV.

Table 1.   Test circuit information.

Table 2.   RV insertion under no constraint with our method.

Table 3.   RV insertion under timing constraint with our method.

Table 4.   RV insertion under timing constraint in Ref. [26].

[1]
Chen Wenbiao, Chen Lan, Li Zhigang, et al. Effects of pattern characteristics on the copper electroplating process. Journal of Semiconductors, 2011, 32(5):055010 doi: 10.1088/1674-4926/32/5/055010
[2]
Yang Yiwei, Shi Zheng, Yan Xiaolang. Model-based dynamic dissection in OPC. Journal of Semiconductors, 2008, 29(7):1422 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=07110903&flag=1
[3]
Liang Tao, Jia Xinzhang. A numerical integration-based yield estimation method for integrated circuits. Journal of Semiconductors, 2011, 32(4):045012 doi: 10.1088/1674-4926/32/4/045012
[4]
Wang Junping, Hao Yue. Yield modeling of rectangular defect outline. Chinese Journal of Semiconductors, 2005, 26(8):1514 http://www.oalib.com/paper/1518454
[5]
Liang Tao, Jia Xinzhang. An empirical formula for yield estimation from singly truncated performance data of qualified semiconductor devices. Journal of Semiconductors, 2012, 33(12):125008 doi: 10.1088/1674-4926/33/12/125008
[6]
Yang Yintang, Leng Peng, Dong Gang, et al. RLC interconnect delay with temperature distribution effects. Journal of Semiconductors, 2008, 29(9):1843 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=07112202&flag=1
[7]
Li X, Wang J M, Tang W, et al. Stochastic analysis of interconnect delay in the presence of process variations. Journal of Semiconductors, 2008, 29(2):304 http://www.jos.ac.cn/bdtxbcn/ch/reader/view_abstract.aspx?file_no=07082201&flag=1
[8]
Barnt T S, Bickford J, Weger A J. Product yield prediction system and critical area database. IEEE Trans Semicond Manufac, 2007, 21(3):351 http://ieeexplore.ieee.org/document/4589022/
[9]
Ducotey G, Couvrat A, Audran V. In-line methodology for defectivity analysis form dark field wafer inspection to defect root cause analysis using FIB cut. Advanced Semiconductor Manufacturing Conference, 2008 http://ieeexplore.ieee.org/document/4529041/?reload=true&arnumber=4529041&punumber%3D4519622
[10]
Izuka T, IkedaM, Asada K. Timing-aware cell layout de-compaction for yield optimization by critical area minimization. IEEE Trans VLSI Syst, 2007, 15(6):716 doi: 10.1109/TVLSI.2007.898754
[11]
Wang J P, Hao Y. Critical area computation for real defects and arbitary conductor shapes. Acta Electronica Sinica, 2006, 34(4):1974 http://cpb.iphy.ac.cn/EN/Y2006/V15/I7/1621
[12]
Beanato G, Giovannini P, Cevrero A. Design and testing strategies for modular 3-D-multiprocessor systems using die-level through silicon via technology. IEEE J Emerging and Selected Topics in Circuits and Systems, 2012, 2(2):295 doi: 10.1109/JETCAS.2012.2193837
[13]
Ting F C, Tsang C K, Shih H Y. Enhanced redundant via insertion with multi-via mechanisms. IEEE Computer Society Annual Symposium on VLSI, 2011 http://ieeexplore.ieee.org/document/5992483/
[14]
Xu G, Huang L D, Pan D Z. Redundant-via enhanced maze routing for yield improvement. Proceedings of the ASP-DAC, 2005 http://dl.acm.org/citation.cfm?id=1120927
[15]
Lee K Y, Koh C K, Wang T C. Fast and optimal redundant via insertion. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2008, 27(12):2194 http://ieeexplore.ieee.org/document/4670066/
[16]
Chen H Y, Chiang M F, Chang Y W. Full-chip routing considering double-via insertion. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2010, 27(5):844 http://dl.acm.org/citation.cfm?id=2301984
[17]
Chang T F, Kan T C, Yang S H. Enhanced redundant via insertion with multi-via mechanisms. The 14th IEEE Computer Society Annual Symposium on VLSI, 2011 http://ieeexplore.ieee.org/document/5992483/
[18]
Kan T C K, Yang S H, Chang T F. Design of a practical nanometer-scale redundant via-aware standard cell library for improved redundant via1 insertion rate. IEEE Trans VLSI Syst, 2013, 21(1):142 doi: 10.1109/TVLSI.2011.2176968
[19]
Yao H L, Cai Y, Zhou Q. Multilevel routing with redundant via insertion. IEEE Trans Circuits Syst, 2006, 53(10):1148 doi: 10.1109/TCSII.2006.881822
[20]
Allan G A. Targeted layout modifications for semiconductor yield/reliability enhancement. IEEE Trans Semicond Manufacturing, 2004, 17(4):573 doi: 10.1109/TSM.2004.835727
[21]
Hao Ran, Wang Huijuan, Yu Daquan, et al. High-speed through-silicon via filling method using Cu-cored solder balls. Journal of Semiconductors, 2012, 33(8):086002 doi: 10.1088/1674-4926/33/8/086002
[22]
Haltmeier M. Stable signal reconstruction via minimization in redundant, non-tight frames. IEEE Trans Signal Processing, 2013, 61(2):420 doi: 10.1109/TSP.2012.2222396
[23]
Shen J W, Chiang M F, Chen S. Redundant via allocation for layer partition-based redundant via insertion. IEEE 8th International Conference on ASIC, 2009 http://ieeexplore.ieee.org/document/5351310/
[24]
Liang J, Chen S, Yoshimura T. Redundant via insertion based on conflict removal. ICSICT, 2010 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5667425
[25]
Luo F, Jia Y, Dai W M. Yield-preferred via insertion based on novel geotopological technology. Asia and South Pacific Conference on Design Automation, 2006 http://dl.acm.org/citation.cfm?id=1118469
[26]
Pan C W, Lee Y M. Redundant via insertion under timing constraints. The 12th International Symposium on Quality Electronic Design, 2011 http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5770794
[27]
Yan J T T, Chen Z W, Chiang B Y. Timing-constrained yield-driven redundant via insertion. APPCCAS, 2008 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4746363
[28]
Yan J T, Chiang B Y, Chen Z W. Yield-driven redundant via insertion based on probalilistic via-insertion analysis. International Conference on Electronics, Circuits and Systems, 2006 http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4263506
[29]
Hao Y. Theory and methods of integrated circuits manufacturing dynamics. Beijing:Beijing Educational Press, 1995:132
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    Junping Wang, Dan Xu, Yongbang Su. A method for timing constrained redundant via insertion[J]. Journal of Semiconductors, 2014, 35(4): 045010. doi: 10.1088/1674-4926/35/4/045010
    J P Wang, D Xu, Y B Su. A method for timing constrained redundant via insertion[J]. J. Semicond., 2014, 35(4): 045010. doi: 10.1088/1674-4926/35/4/045010.
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    Received: 11 May 2013 Revised: 25 November 2013 Online: Published: 01 April 2014

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      Junping Wang, Dan Xu, Yongbang Su. A method for timing constrained redundant via insertion[J]. Journal of Semiconductors, 2014, 35(4): 045010. doi: 10.1088/1674-4926/35/4/045010 ****J P Wang, D Xu, Y B Su. A method for timing constrained redundant via insertion[J]. J. Semicond., 2014, 35(4): 045010. doi: 10.1088/1674-4926/35/4/045010.
      Citation:
      Junping Wang, Dan Xu, Yongbang Su. A method for timing constrained redundant via insertion[J]. Journal of Semiconductors, 2014, 35(4): 045010. doi: 10.1088/1674-4926/35/4/045010 ****
      J P Wang, D Xu, Y B Su. A method for timing constrained redundant via insertion[J]. J. Semicond., 2014, 35(4): 045010. doi: 10.1088/1674-4926/35/4/045010.

      A method for timing constrained redundant via insertion

      DOI: 10.1088/1674-4926/35/4/045010
      Funds:

      the Programme of Introducing Talents of Discipline to Universities B08038

      Project supported by the National Natural Science Foundation of China (No. 61173088) and the Programme of Introducing Talents of Discipline to Universities (No. B08038)

      the National Natural Science Foundation of China 61173088

      More Information
      • Corresponding author: Wang Junping, Email:jpwang@mail.xidian.edu.cn
      • Received Date: 2013-05-11
      • Revised Date: 2013-11-25
      • Published Date: 2014-04-01

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