Fig. 1.
(a) Bulk CMOS structure. (b) SOI CMOS structure.
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Lingjuan Lü, Ruping Liu, Min Lin, Zehua Sang, Shichang Zou, Genqing Yang. Performance comparison of radiation-hardened layout techniques[J]. Journal of Semiconductors, 2014, 35(6): 065006. doi: 10.1088/1674-4926/35/6/065006
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L Lü, R P Liu, M Lin, Z H Sang, S C Zou, G Q Yang. Performance comparison of radiation-hardened layout techniques[J]. J. Semicond., 2014, 35(6): 065006. doi: 10.1088/1674-4926/35/6/065006.
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Performance comparison of radiation-hardened layout techniques
DOI: 10.1088/1674-4926/35/6/065006
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Abstract
Total ionizing dose (TID) effect and single event effect (SEE) from space may cause serious effects on bulk silicon and silicon on insulator (SOI) devices, so designers must pay much attention to these bad effects to achieve better performance. This paper presents different radiation-hardened layout techniques to mitigate TID and SEE effect on bulk silicon and SOI device and their corresponding advantages and disadvantages are studied in detail. Under 0.13 μm bulk silicon and SOI process technology, performance comparisons of two different kinds of DFF circuit are made, of which one kind is only hardened in layout (protection ring for bulk silicon DFF, T-gate for SOI DFF), while the other kind is also hardened in schematic such as DICE structure. The result shows that static power and leakage of SOI DFF is lower than that of bulk silicon DFF, while SOI DFF with T-gate is a little slower than bulk silicon DFF with protection ring, which will provide useful guidance for radiation-hardened circuit and layout design. -
References
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