1. Introduction

With the dramatic progress of semiconductor technology, modern communication is evolving towards ultra-high-speed wireless communication systems. Since the 60 GHz band millimeter wave technology enables transceivers to transmit the data in a several Gb/s data rate, high-speed DAC has become an important part of the 4th generation of wireless communications and has been widely applied in short distance transmission fields, including WLAN, WPAN, ad-hoc network and point-to-point link etc. Moreover, high-speed DAC are widely used in UWB applications. In UWB systems that adopt MB-OFDM technology, the spectrum from 3.1 to 10.6 GHz is divided into 14 channels, each with 528 MHz channel bandwidth, hence the sampling rate should be higher than 1.056 GS/s. In DS-CDMA UWB technology, the highest data rate is 1.35 Gbps, so the three times over-sampling of the data signal requires the DAC to operate at 4 GS/s. Consequently a DAC that is applicable in multimode communication systems and operates at 4 GS/s becomes the design target of this paper.

In the last decade, intensive research has been conducted on high-speed DAC. Reference [1] simulated a 6-bit 5.4 GS/s CMOS DAC based on IBM 0.13 $\mu$m CMOS technology, which employed two-stage current-steering topology to balance the resistive and capacitive loads and utilized the folded-cascode current source cell to eliminate the need to control the crossing point of the switch, however, the DNL error of the DAC with 0.26 LSB is not so good. In Ref.[2] a pseudo-segmentation decoding method was proposed to improve dynamic performance instead of a traditional thermometer decoding. Compared to the pseudo-segmentation decoding method, a better solution called pseudo-thermometer decoding method in Ref.[3] is chosen to tackle the large current source area issue that exists in the pseudo-segmentation decoder. The high conversion rate, low power consumption and the relatively low $f_{\rm T}$ based on the standard 0.18 $\mu$m CMOS technology all make the design a challenge. In this paper, we propose a paradigm for a high-speed and power-efficient 6-bit DAC with the operating rate up to 4GS/s. As we aim for a very high conversion rate, a novel '2T+4B' pseudo-thermometer decoding architecture is applied for the 4 GS/s high-speed design of DAC. This brings about better dynamic performance of the converter, together with an enhancement of operation speed and reduction of power dissipation. Additionally, a high-speed and single-phase with high crossing point latch structure is utilized to avoid simultaneously turning off the following differential switches^[2]. As the layout arrangement for high-frequency circuits is of great significance, cost-effective floor planning and various layout techniques including tree-like routing, cross-quading method and common-centroid principal are employed to satisfy the high-speed and matching requirements.

2. Architecture

In terms of the digital decoding method, a segmented decoder strikes a perfect balance between the merits and flaws of the binary and thermometer implementations, therefore it is preferred and being widely adopted in various applications. Since the design targets low-resolution and high-speed DAC with good static and dynamic performances, finally the segmented implementation becomes the optimal choice. The proposed block diagram of the designed 6-bit pseudo-thermometer segmented DAC is illustrated in Fig. 1.

2.1 Pseudo-thermometer-segmented decoder

Generally, the static performance of a DAC is evaluated by standard deviation of DNL ($\sigma$(DNL)) and INL ($\sigma$(INL)). According to statistical analysis, the maximum $\sigma$(DNL) and $\sigma$(INL) for single-ended output DAC can be estimated by the following equations^[4]:

$\sigma ({\rm DNL})_{\rm max} =\sqrt {2^{B+1}-1} \frac{\sigma (I)}{I} \quad ({\rm LSB}),$

(1)

$\sigma ({\rm INL})_{\rm max} =0.5\sqrt {2^N-1} \frac{\sigma (I)}{I} \quad {\rm (LSB)},$

(2)

where $N$ is the resolution of the DAC, $B$ is the number of the binary-weighted bits of the DAC, and $\sigma (I)/I$ is the standard deviation of a unit current source. $B$ in Eq. (1) is valid only when it is less than or equal to $N$ -1. Equations (1) and (2) show that for a 6-bit DAC, the DNL error will constrain the static performance when $B$ the binary-weighted bits number of a 6-bit DAC is larger than 3; on the other hand, the INL error becomes a constraint when $B$ is less than or equal to 3. As the required output impedance for fully differential drops by over an order of magnitude for both INL and spurious performance, to leave enough headroom, we still adopt Eqs. (1) and (2) for the design of fully-differential DAC in this paper. Additionally, taking the cost, power efficiency and operating speed into consideration, more thermometer-coded bits means more complex architecture of decoder and heavier clock loading while more binary-weighted bits will substantially reduce the area of current source cells and simplify the architecture of the digital part, but suffers from mismatch errors which will worsen static performance of the DAC^[6]. Therefore, '2T+4B' architecture is chosen in decoder designing to optimize the balance between cost and performance.

Figure 2 shows the proposed architecture of a 3-bit pseudo-thermometer-segmented decoder. The designed DAC performs both a good balance of synchronization between different binary-weighted bits in the thermometer decoder and better matching property than the pseudo-segmentation decoder, meanwhile, it exhibits the same property of the '2T+4B' segmented architecture.

2.2 The Giga-latch circuit

The fundamental functions of the latch array are resynchronization of the digital and switch-controlled signal of different-weighted bits and decreasing the glitches in the signal. In order to avoid the case that differential switches of the latch are turned off simultaneously, resulting in undesirable glitches, an optimized high-crossing-point differential outputs of the latch is expected. Additionally, considering the applied 0.18 $\mu$m CMOS process and low power consumption target, a low-power supply, single-phase and high-speed Giga-latch should be designed. The designed latch block is displayed in Fig. 3, thus a fast rise time of the latch circuit is obtained resulting in the desirable high-crossing-point differential outputs. The small invertors at the bottom used for feedback can reasonably suppress the clock feedthrough by the pass transistors and can effectively stabilize the synchronization of the signals.

2.3 Switched current cell

Current-steering structure is an ideal solution to realize high-speed digital signal to analog signal conversion. The current sources, cascodes and switches are usually designed as an entirety, called switched current cell, as is shown in Fig. 4.

Since the design targets for DAC with high linearity, the switched current cell is vitally important. It is expected to provide well-defined currents and well-controlled switching behavior over the entire operating frequency range. Therefore numerous parameters should be taken into consideration. In the presented design, the total output current was chosen to be 4 mA, and the load resistor is set to be 50 $\Omega$, this results in a single ended output swing of 200 mV. The current source transistors should exhibit sufficient static matching as well as high impedance up to the desired Nyquist frequency, thus avoiding nonlinearities originating from signal-dependent output impedance. In that case, a cascoded current source is used and the relationship between current cell output impedance and DAC static (INL) and dynamic performance (SFDR) can be summarized by the following two equations^[1]:

${\rm INL}=\frac{I_{\rm o} R_{\rm L}^2k^2}{4R_{\rm imp}},$

(3)

${\rm SFDR}=20 \lg \frac{4R_{\rm imp} }{2^NR_{\rm L}},$

(4)

where $N$ is the number of bits of dynamic range required, $k$ is assumed to be 2$N$, $R_{\rm L}$ is the load resistor, and $R_{\rm imp}$ is the output impedance. According to Eqs. (3) and (4), we can estimate that the required output impedance $R_{\rm imp}$ should be 12.8 M$\Omega$ for 10-bit INL and 50.5 k$\Omega$ for 6-bit SFDR up to the Nyquist frequency. The static accuracy of the converter, usually measured by DNL and INL, is decided by the matching properties of the current source transistors. Furthermore, random errors and systematic errors exert profound influence on the static property of the current source array. To reserve a safety margin for the 6-bit DAC design, we set the standard deviation specification to be 0.5% with 10-bit static accuracy for 99.7% yield. Referring to the well-known relation between area and mismatch current source transistors, formulated in Eqs. (5) and (6), the physical dimensions of the current source transistors can be estimated^[8].

$WL=\left[A_\beta ^2+\frac{4A_{\rm VT} ^2}{(V_{\rm gs}-V_{\rm th})^2}\right]\Bigg/2\left(\frac{\sigma (I)}{I}\right)^2,$

(5)

$\frac{W}{L}=\frac{2I_{\rm FS} }{{\rm KP} (2^N-1) (V_{\rm gs} -V_{\rm th})^2},$

(6)

where KP is a technology-based parameter.

In the presented design, $V_{\rm gs}$ -$V_{\rm th}$ is chosen to be 0.13 V, the gate-length and gate-width of current source transistors in the switched current cell are set to be 2.3 $\mu$m and 43.7 $\mu$m for a 10-bit accuracy specification. Figure 5 proposes a novel floor plan method of the current source array based on common-centroid switching distribution.

3. Layout

Layout of the designed 6-bit DAC is displayed in Fig. 6. In terms of high frequency mixed signal integrated circuits, layout considerations including floor planning and techniques are vitally important. In this paper, differential routing is adapted after decoding to enhance noise immunity. Compactness of the digital part is desirable to reduce the propagation delay and power dissipation. Moreover, tree-like structure of the clock chain and output is utilized to synchronize the high-speed multi-signals. For high-speed DAC, parasitics, especially parasitic capacitance, cannot be ignored in the layout design. Splitting devices and source-drain sharing will largely reduce the parasitics on CMOS transistors, thus reducing the RC time constant and improving device speed. As the higher the frequency of a signal, the easier it will pass through a capacitor, we make the best of the white space and fill them with big capacitors across the power rails, then any noise that gets zapped into the power rail will preferentially be sucked down to the ground. Furthermore, by employing stacked power and ground rails, some amount of free capacitors for decoupling the power rails are obtained in a much smaller space. In addition, from the matching point of view, good layout will immensely enhance both the static performance and dynamic performance. Therefore, cross-quading techniques are used in the switch layout design and dummy devices together with common-centroid techniques are applied in the current source array design. While random errors can be reduced by increasing the area of the matched transistors, systematic errors, which mainly originate from gradient-induced mismatch errors and edge effect, can be effectively mitigated by adapting common-centroid switching distribution method and placing dummy cells around the current source array in the layout design. In order to optimize the arrangement of the layout, the second LSB current source is chosen to be the unit of the current source array; in that case, there are altogether 32 operational current source cells and 64 dummy cells in the current source array. Finally, a number of guard rings are separately placed around the current source array and the digital module so as to eliminate interference between analog signal and digital signal. ESD protection is also considered in the schematic and layout design as is shown in Fig. 6.

4. Post simulation results

Figure 7 shows the layout of the designed DAC in the paper. The area of the core circuit is 0.4 $\times$ 0.5 mm$^{2}$. All the simulations are performed on differential outputs with full scale input signals. The simulated static linearity performance including DNL and INL is shown in Fig. 7. From Fig. 7, we can see the DNL of the DAC is within $\pm$0.28 LSB and the INL is within $\pm$0.26 LSB, which can fulfill the design target.

Figure 8 shows the spectrum of the differential output signals under 4 GS/s update rate with near-Nyquist sampling. Figure 8 demonstrates the 6-bit dynamic performance of the designed DAC is 40.83 dB for a 1.9 GHz sinusoidal output signal. The DAC can operate well when the frequency of clock signal or sinusoidal output signal varies. SFDR are respectively 34.39 dB and 42.26 dB when the frequency of output signal is 968.7 MHz and 531.2 MHz under 4 GS/s update rate. For near-Nyquist sampling with the update rate 2 GHz and 1 GHz, SFDR of the DAC are respectively 44.61 dB and 40.38 dB. Data of SFDR shows the DAC system has good dynamic performance.

Definition of figure of merit (FOM) in Eq. (5) aims at evaluating the cost-effective performance of high-speed DACs^[1].

${\rm FOM}=\frac{\rm Power}{2^N\cdot {\rm SamplingRate}}.$

(7)

According to Eq. (5), we can estimate the FOM of the designed DAC, when the update rate is 4 GS/s, FOM of the 6-bit DAC with 35 mW power dissipation is about 146 fJ/conv.-step.

5. Comparison with other high-speed D/A converters

Table 1 summarizes parameters of DAC systems and makes comparisons between related published articles on 6-bit high-speed DAC with this work.

Table 1 demonstrates that in specified CMOS technology, the 6-bit high-speed DAC presented in this work reflects both good static and dynamic performances with the update rate up to 4 GS/s. Comparing to Refs.[2, 5, 13], this work largely increases the highest sampling rate of DAC and its SFDR stays high even when 4 GS/s near-Nyquist sampling, INL and DNL are well-balanced, so the static performance of this work is better than Ref.[2], but worse than Refs.[5] and [13]. Considering the high update rate, the power and FOM are relatively moderate. In terms of active area, this work is not as compact as the design in Refs.[5] and [13]; improvements can be made by adopting new architecture or advanced technology.

6. Conclusion

A 6-bit 4GPS pseudo-thermometer segmented CMOS DAC fully functional ranging from DC to near-Nyquist sampling is presented in this paper. The designed DAC is cost-effective and displays both good static and dynamic performances. DNL and INL errors are controlled within 0.28 LSB, SFDR is 40.83 dB under 4GHz near-Nyquist sampling. The DAC is designed in a standard 0.18 $\mu$m CMOS technology with an active area of 0.2 mm$^{2}$. The power dissipation at 4 GHz clock frequency for a 1.906 GHz near-Nyquist sinusoidal output signal is less than 37 mW. Post simulation results show the presented DAC fulfill the requirements of wireless transceiver systems based on both OFDM and CDMA UWB technology and fit in the sub-gigahertz LR-WPAN applications.