Fig. 1.
SiC MOS normalized $C$ -$V$ curves with different annealing conditions.
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| Citation: |
Hongli Yan, Renxu Jia, Xiaoyan Tang, Qingwen Song, Yuming Zhang. Effect of re-oxidation annealing process on the SiO2/SiC interface characteristics[J]. Journal of Semiconductors, 2014, 35(6): 066001. doi: 10.1088/1674-4926/35/6/066001
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H L Yan, R X Jia, X Y Tang, Q W Song, Y M Zhang. Effect of re-oxidation annealing process on the SiO2/SiC interface characteristics[J]. J. Semicond., 2014, 35(6): 066001. doi: 10.1088/1674-4926/35/6/066001.
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Effect of re-oxidation annealing process on the SiO2/SiC interface characteristics
DOI: 10.1088/1674-4926/35/6/066001
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Abstract
The effect of the different re-oxidation annealing (ROA) processes on the SiO2/SiC interface characteristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance-voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050℃ for 30 min, while a large number of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy (XPS) testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process. -
References
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