1. Introduction

The medium-resolution, fast-speed and low-power analog-to-digital converters (ADCs) play a significant role in the realm of energy-limited applications, such as the wireless sensor network (WSN) and portable devices. The flash ADC employs the parallel structure, and thus acquires fast conversion. However, its power consumption and hardware cost increase exponentially with the precision. On the contrary, the successive approximation register ADC (SAR ADC), which accomplishes its conversion based on binary-search algorithm and merely applies one comparator, is superior in lower power and smaller area^{[1, 2]}. Furthermore, with the progressing of CMOS technology and the scaling down of feature size, the SAR ADC, almost fully consisting of digital modules, is more ascendant than other ADCs in the deep sub-micron design, which are mainly composed of analog blocks and unsuitable for process migration. In recent years, the high-speed and low power SAR ADC has flourished gradually. In 2006 JSSC^[3], a 6-bit 600 MS/s asynchronous SAR ADC was achieved by time-interleaving two channels, which adopted the asynchronous control logic and improved the conversion efficiency. In 2010 TCAS-I^[4], a 5-bit 800 MS/s binary-search ADC was presented in a single channel, which integrated the merits of flash ADC and SAR ADC through utilizing a resistive digital-to-analog converter (DAC). In 2012 JSSC^[5], a 6-bit 1250 MS/s SAR ADC fabricated in 40 nm CMOS was realized in a single channel, which employed $N$ comparators and asynchronous feedback delay processing. According to the development trend of the high speed SAR ADC, the asynchronous control timing makes for improving the conversion efficiency, in which the comparator actualizes triggering the adjacent stage without synchronous control logic and thus eliminates the time wasting in comparator arbitrating^[3]. Furthermore, the combination of different structure ADCs is a feasible approach for fast-speed design, such as employing the full parallel technique of the flash ADC in the binary search algorithm of the SAR ADC.

This paper proposes a modified asynchronous SAR ADC, which converts two bits per stage and merely requires three stages to achieve 6-bit resolution. The four-ended dynamic comparator is adopted, which only consumes dynamic power without static path. Meanwhile, the compact and symmetrical layout is designed in order to minimize the effects of the parasitic parameter and technology mismatch. Furthermore, so as to diminish the clock jitter and accelerate the establishment of the clock signal, a clock buffer is applied, which is achieved through the double-to-single amplifier.

2. Design of asynchronous SAR ADC

The conventional SAR ADC in Fig. 1 mainly contains the sample and hold (S/H) circuit, the DAC, the comparator and the SAR control logic. Its conversion process conforms to the binary-search algorithm. First of all, the input signal is sampled and held by the S/H. The DAC outputs the reference voltages through charge redistribution, which is dominated by the SAR control logic. The comparator arbitrates between the held input voltages and reference voltages. The arbitrating result modulates the control logic conversely and triggers the next clock cycle. In the synchronous SAR ADC, an $N$-bit ($N$ is the resolution) design needs $N$ clock cycles to achieve a full conversion^{[6, 7]}. The conversion time of each bit is equal and needs to tolerate the lowest conversion. Accordingly, the whole conversion time includes four parts: the time of S/H stage, the time of comparator arbitrating, the time of DAC charge redistribution, and the time of control logic, as described in Eq. (1):

$ \begin{equation} T_{\rm TOTAL}=T_{\rm S/H}+NT_{\rm COMP}+T_{\rm LOGIC}. \end{equation} $

(1)

In order to reduce the conversion time and enhance the sampling rate, the asynchronous control logic is usually employed in high-speed SAR ADC^[3]. In the administration of the asynchronous timing, the comparator actualizes the triggering of adjacent stages from the most significant bit (MSB) to the least significant bit (LSB), and does not have to endure the slowest comparison, the whole conversion time changes to Eq. (2):

$ \begin{equation} T_{\rm TOTAL}=T_{\rm S/H}+\sum\limits_{\rm LSB}^{\rm MSB}T_{\rm COMP}+T_{\rm DAC}+T_{\rm LOGIC}. \end{equation} $

(2)

An approach that elevates the conversion efficiency of the foresaid asynchronous SAR ADC, is to optimize the critical path and simplify the logic circuit. Another way is combining the SAR ADC and flash ADC, as presented in Ref. [4], which utilizes the resistance array to generate reference voltages directly, and thus saves the time of DAC charge redistribution. The whole conversion time converts to Eq. (3):

$ \begin{equation} T_{\rm TOTAL}=T_{\rm S/H}+\sum\limits_{\rm LSB}^{\rm MSB}T_{\rm COMP}+T_{\rm LOGIC}. \end{equation} $

(3)

However, the design in Ref. [4] merely exports one bit per stage, and a full conversion needs six stages. In order to advance the conversion efficiency, a feasible method is proposed to increase the output bits per stage^[8,9]. This paper supplies a modified 6-bit SAR ADC, as depicted in Fig. 2(a), which comprises three stages with two bits conveyed in each stage. Taking the first stage for instance, it is required to compare three reference voltages, the 0, 1/2 and -1/2, respectively, and therefore three active comparators are utilized simultaneously as shown in Fig. 2. According to comparison results of the first stage, the data decoder calculates the outputs D5, D4, and the asynchronous logic generates the trigger signal's next stage and setting signals of switching network. Figure 2(c) shows the logic circuit that is used to engender the setting signals. The summation of the operation time cost by the second stage's comparator and the establishing time of the third stage trigger signal needs more than the setting time of the third stage reference voltages, so as to meet the accurateness of the third stage reference voltages. The time deviation in adjacent stages is vital to asynchronous logic circuit, and thus decreasing the stage count is propitious. This design only needs three stages, boosts the conversion speed and whittles the destabilization of asynchronous logic. Equation (4) describes the conversion time of this proposed structure.

$ \begin{equation} T_{\rm TOTAL}=T_{\rm S/H}+T_{\rm COMP, \, ST1}+T_{\rm COMP, \, ST2}+T_{\rm COMP, \, ST3}+T_{\rm COGIC}. \end{equation} $

(4)

3. Circuit implementation

3.1 Sample and hold circuit

The sample and hold circuit implemented by the transmission gate switch is vital to guarantee the design performance, and therefore the influence of clock feedthrough and employment of the dummy fingers are taken into consideration to maintain the exactitude of the S/H voltage. According to Eq. (4), the time of sample and hold stage is crucial to the time optimizing, which depends on the multiplying of the switch resistance and the held capacitance. Increasing the size of the transmission gate can lessen the switch resistance, but nevertheless enlarges the transistor capacitance. Thus the selection of the sizes of the switch and held capacitance needs to compromise between the time saving and the driving capability based on the whole ADC design. Meanwhile, the sampling clock buffer is designed to minimize the clock jitter, which has great impact on the performance of the high-frequency ADC. Accomplishing through the double-to-single amplifier^[10], the buffer is able to tolerate minor swing amplitude, which is propitious for establishing the clock signal and weakening the impact of the bonding wire.

3.2 Resistive DAC

The typical DAC array is classified into capacitive DAC and resistive DAC. In the traditional 6-bit SAR ADC, the capacitive DAC usually adopts binary-weighted capacitor array^[7]. For the sake of realizing fast-speed ADC, the capacitor demands a smaller value to curtail the charge redistribution time of capacitive DAC. However, the reduction of the capacitance worsens the matching accuracy of DAC array and depresses the performance. The conventional resistive DAC that generates the entire reference voltages at the beginning of the ADC operation, is usually used in the high-speed flash ADC. However, the synchronous SAR ADC, which only has one comparator to achieve periodic conversion, is unable to arbitrate all the reference voltages synchronously. In this modified SAR ADC as shown in Fig. 2, utilizing asynchronous control logic, three comparators per stage and switching array makes the resistive DAC available. Moreover, the dummy resistance and decouple capacitor are employed in order to benefit the etching atmosphere and stabilize the reference voltages^[4].

3.3 Four-ended dynamic comparator

The analog blocks dominate the power consumption of data converters. The comparator, as the only analog module in SAR ADC, is the chief origin of the system power. The conventional static comparator contains a preamplifier, which consumes considerable static power. Moreover, it requires taking the gain and bandwidth into account, which is susceptible to the bias condition. This proposed SAR ADC utilizes the four-ended dynamic comparator in Fig. 3, which merely consumes dynamic power without static path^[4] and has a robust immunity to the deviation of the technology. Meanwhile, Equation (4) indicates that the time consumed by the comparator is the primary part of the total conversion time. Unlike the static comparator with a preamplifier, the dynamic comparator is based on the regenerative feedback latch, which accelerates the arbitrating of the comparator. While the clock signal CLK is low, the comparator is reset. When the CLK is high, the comparator begins to operate. The transistors M1/M2 turn on. The bigger one between the difference of voltages VIN1/VIN2 and the difference of voltages VREF1/VREF2 would activate the regeneration circuit first^{[11, 12]}. The cross-couple inverters export the comparison results. By utilizing the high energy efficiency four-ended dynamic comparator, this presented SAR ADC accomplishes 0.93 mW power consumption at 230-MS/s sampling rate.

3.4 SAR control logic

In the synchronous 6-bit SAR ADC, the control logic as the scheduling block supplies the whole system control signals, including the system reset signal, system clock signal and one feedback signal^[13]. It ensures that the charge distribution of DAC array and the arbitrating of comparator operate accurately. The uniform control timing is stable, whereas an $N$-bit synchronous SAR ADC requires $N$ clock cycles to accomplish the whole conversion^[14]. As shown in Fig. 4(a), the operation of each bit is equally-timed from MSB to LSB, which results in the time wasting in order to accommodate the slowest comparison. Moreover, the synchronous clock signal operates at least $N+$ 1 times of the sampling rate, which puts forward a strict demand for the test instruments^[15]. For instance, this proposed 6-bit 230-MS/s SAR ADC would require a 1.61-GHz external clock. The clock jitter of such a high-frequency signal is considerable and the power consumption of synthesizing the clock signal would be more than the ADC itself. Accordingly, the synchronous timing is generally adopted in low-frequency and high-resolution SAR ADC.

The asynchronous control logic as displayed in Fig. 4(b), is more appropriate for high-speed design^[16,17]. Firstly, the external clock of asynchronous SAR ADC is equal to the sampling rate, which relaxes the requirement to the test devices and shrinks the power consumption in the clock circuit. Additionally, the asynchronous timing operates like dominos from MSB to LSB and eliminates the conversion time wasting. In this proposed 2 bits/stage structure of Fig. 4(c), while the conversion of the first stage is done, the second stage starts to perform and the reference voltages of the third stage are preset simultaneously. Through increasing the output bits per stage, the conversion efficiency elevates. Meanwhile, the lessening of the number of output stages is beneficial for eliminating the timing bias between former and latter stages and enhancing the stability of the asynchronous timing.

4. Measurement results

Fabricated in SMIC 65-nm technology, the die photograph of this proposed SAR ADC is depicted in Fig. 5. Through employing the 2 bits/stage asynchronous control logic, the design reaches a peak SFDR of 40.90-dB and SNDR of 29.05-dB with 191.7 kHz input frequency at 230-MS/s sampling rate as depicted in Fig. 6, and a peak SFDR of 38.17-dB and SNDR of 26.71-dB with 14.1 MHz input frequency at 200-MS/s sampling rate as shown in Fig. 7. Relying on a power efficient dynamic comparator, the SAR ADC only has power consumption of about 0.93 mW at 230-MS/s. In order to assess the overall performance, the figure-of-merit (FOM) is calculated as Eq. (5). The FOM at 230-MS/s is 174.67 fJ/step.

$ \begin{equation} {\rm FOM}=\frac{\rm Power}{2^{\rm ENOB} \times f_{\rm s}}. \end{equation} $

(5)

Figure 8 illustrates the measurement setup of this prototyped SAR ADC, which is mounted on a typical four-layer printed circuit board (PCB). The sampling clock is supplied by the Agilent N5181A, and the power supply is provided by the Agilent E3631A. The Stanford Research Systems DS360 generates the low frequency differential input signals, and the Agilent E4438C and the bandpass filter are utilized for high frequency input signals. The $N$ bits output data are collected by the logic analyzer Agilent 16823A and processed by the MATLAB software. During testing the chip, the bandpass filter is essential to achieve high linearity and eliminate the distortion of the high frequency input signals. Moreover, increasing the decouple capacitors on the back of the test PCB and shortening the bonding wire are advantageous for progressing the circuit performance^{[7, 18]}.

Table 1 summarizes the measurement performance of this design and compares with other designs. In a single channel, this ADC works at 230-MS/s sampling rate with 40.90-dB SFDR and power consumption less than 1 mW at 1 V power supply. Through comparing with the international leading journals in circuit and system, such as Journal of Solid-State Circuits (JSSC) and Transactions on Circuits and Systems (TCAS), the sampling rate of this work has a great distance. Our research group focuses on the low power and high speed SAR ADC in recent years, the design chip is from the 6-bit 20-MS/s synchronous SAR ADC in HJTC 180 nm^[7] to the 6-bit 230-MS/s asynchronous SAR ADC in SMIC 65 nm. The advanced process and circuit structure are adopted to increase the sampling rate, whereas some factors still restrict improvement of the conversion speed. Firstly, the parasitic parameters including the parasitic resistance and capacitance severely deteriorate the sampling rate, which almost decreases twenty percent compared with the simulation result. Therefore more compact layout design and distribution would be employed in the future work. Secondly, the circuit structure still has the optimizing space. In order to ensure establishing the differential input signals, this design provides the sufficient time for the S/H stage and leaves some margin, which restricts the conversion speed. Meanwhile, establishing the reference voltages is also based on the same consideration. However, this proposed ADC still possesses significant value in the following fast-speed design. It is suitable for time-interleaving, because the reference voltages are generated by resistive array directly. Therefore, the sub-ADC could share one DAC, which economizes the chip area and makes for decreasing the channel mismatch. For the time-interleaving of $N$ channel sub-ADCs, the sampling rate would increase $N$ times. In the future work, the time-interleaving technology would be utilized to achieve faster speed design.

5. Conclusion

An asynchronous and differential-ended 6-bit 230-MS/s modified SAR ADC is implemented in SMIC 65-nm-CMOS. Based on the modified two bits/stage asynchronous timing and four-ended dynamic comparator, this proposed ADC achieves 40.90-SFDR and 29.05-SNDR in a single channel, and merely consumes 0.93 mW at 1 V power supply, corresponding to an FOM of 174.67 fJ/step.