1. Introduction

Light-emitting diodes (LEDs) have been widely used in indicator, display, back lighting, and general lighting applications. One promising way to improve light-output power of LED chips is surface texturing^[1], which can enhance the probability of lights entering the escape cone on the interface between semiconductor and package materials. In conventional configuration of LED chips with insulating sapphire substrate, the lights emitted from a multiple quantum well (MQW) would pass through a p-type GaN layer and then escape. Generally, in order to improve the current-spreading performance, the top surface of p-type GaN is covered by an indium-tin-oxide (ITO) layer, since the conductivity of p-type GaN is much lower than that of ITO. Thus, the surface-texturing techniques in conventional LED chips are mostly developed for the ITO layer.

The micro-textured pattern, which can be defined by standard photolithography, was proposed first^[2-4]. However, it was found that the optimum size for surface texture should be of the order of the wavelength of light in semiconductor materials, and then the nano-texturing attracts much attention^[5-14]. Periodic distributed nano-structure can be obtained via electron-beam lithography, imprint lithography^[5], and laser holographic lithography^[6]. The randomly distributed nano-structure can be realized by natural lithography, in which the mask for etching is spin-coated polystyrene spheres^[7] or Ni nano-particles^[8], or the mask is the distorted photoresist during inductively coupled plasma (ICP) etching process^[9]. However, these techniques have not been suitable for mass-production up to now. A promising method for randomly distributed nano-structure is the maskless wet-etching technique^[10-14]. The ITO thin-film deposited by electron-beam evaporation is polycrystalline and consists of grain-like particles. The weak binding energy at the grain boundary facilitates the formation of nano-structures.

In this paper, a hybrid texturing pattern combining micro-and nano-structures was proposed. The nano-structure on the ITO surface was realized at first by maskless wet-etching, and then the micro-structure was achieved by standard photolithography and wet-etching. In addition, the micro-structure was in the form of concave or convex, depending on whether positive or negative photoresist was used in the photolithography process.

2. Experiments

All samples were prepared in a mature product line for conventional LED chips. The LED epitaxial wafers were grown on $c$-plane (0001) patterned sapphire substrate (PSS) by metal-organic chemical vapor deposition (MOCVD). The epilayer structure consists of a 30 nm-thick GaN buffer layer, a 2.3 $\mu$m-thick unintentionally doped GaN layer, a 2.4 $\mu$m-thick Si-doped n-type GaN layer, eighteen pairs of 2.5 nm/12.5 nm-thick InGaN/GaN MQWs, a 30 nm-thick p-type AlGaN electron barrier layer, and a 300 nm-thick Mg-doped p-type GaN layer.

The LED chips with micro/nano-textured ITO surface were fabricated as follows and the main steps are shown in Fig. 1. Firstly, the expilayer was partially etched by ICP to expose n-type GaN layer for mesa structure. Secondly, a SiO$_{2}$ layer was deposited by plasma-enhanced chemical vapor deposition (PECVD) and wet-etched as current blocking layer (CBL)^[15]. Thirdly, a 230 nm-thick ITO was deposited by electron-beam evaporation as transparent conductive layer. In the evaporation process, the ITO pallets, which were composed of 90 wt% In$_{2}$O$_{3}$ and 10 wt% SnO$_{2}$, were evaporated at a temperature of 300 ℃ and a pressure of 10$^{-6}$ Pa, while the flow rate of O$_{2}$ was 10 sccm and the deposition rate of ITO was set to be 0.05 nm/s. Subsequently, the as-deposited ITO layer was wet-etched in a solution of ITO etchant at a temperature of 50 ℃, and the etching time is 10 s. Here, no etching mask was used, and the entire ITO surface was directly in contact with the etchant, which consists of HCl, FeCl$_{3}$, and deionized water. The HCl is the main component for etching, while the FeCl$_{3}$ is to enhance the etching rate and stability. After the maskless wet-etching, a thin-film of positive or negative photoresist was spin-coated, and was treated by standard photolithography. In the photolithography process, a lithography mask with micro-structure was used. The micro-structure is a triangle-lattice of close-packed micro-holes, in which both the diameter and the pitch are 3 $\mu$m. This value of 3 $\mu$m is limited by the accuracy of ultraviolet exposure. Once the photoresist was developed, the triangle-lattice of close-packed micro-holes (concave pattern) or micro-pillars (convex pattern) was formed. The presentation of concave pattern or convex pattern depended on whether positive or negative photoresist had been used. Thereafter, the ITO layer was wet-etched for 7 s, and thus the micro-pattern in the photoresist was transferred onto the ITO surface. The patterned ITO was thermally annealed at 520 ℃ for 25 min while the flow rate of pure N$_{2}$ gas was 20 L/min. After that, the 500 nm/500 nm/12000 nm-thick Cr/Pt/Au multiple metal films were deposited, and the metal lift-off technology was used to fabricate p-type electrodes and n-type electrodes. Then, a 70 nm-thick SiO$_{2}$ layer was deposited by PECVD for passivation, and was wet-etched to expose the electrode pads for wire-bonding. Finally, the sapphire substrates were lapped down to about 100 $\mu$m, and the 2 inch-diameter wafer was diced into 10 mil $\times$ 23 mil chips by laser-scribing and breakage.

Following the above described fabrication process, four types of LED chips were prepared. The first type is the conventional LED chip with as-deposited flat ITO surface (i.e. flat samples). The second type is the LED chip with nano-textured ITO surface after maskless wet-etching (i.e. nano-textured samples), while the third and the fourth types are those with hybrid micro/nano-textured ITO surface (i.e. hybrid-textured samples). The micro-structures in the third and the fourth types of samples are in the form of concave and convex pattern (i.e. concave-hybrid-textured samples and convex-hybrid-textured samples), respectively.

3. Results and discussion

For each of the four types of LED chips, 116 samples are fabricated. The ITO surface morphology was featured by scanning electron microscope (SEM), and the electrical and optical properties of LED chips were measured through a probe station and integrating sphere.

Figure 2 shows the SEM images of the ITO surface in the four types of fabricated samples. It is shown that the surface of the as-deposited ITO is not absolutely smooth. In fact, lots of grain-like particles can be found. Due to the weak binding energy at the grain boundary and the polycrystalline property^[10-14], the size of the grain-like particles grew after maskless wet-etching. On the ITO surface of hybrid-textured samples, the diameter of the micro-hole and micro-pillar is about 3.2 $\mu$m and 2.4 $\mu$m, respectively. The discrepancy between the measured results and the nominal value of 3 $\mu$m determined by the lithography mask can be attributed to the isotropic wet-etching and the error of photolithography. According to the wet-etching test in advance, the etching-rate is estimated to be 7.4 nm/s, and thus the etching depth for the micro-pattern is around 51.8 nm, which is about 1/4 of the thickness of the as-deposited ITO layer.

The typical values of forward voltage at different injection current of the four types of samples are shown in Fig. 3. It is shown that the textured ITO surface would induce a higher forward voltage than the flat ITO surface. This results from the reduced effective thickness of the ITO layer and thus the elevated sheet resistance. Moreover, the hybrid-textured samples have higher forward voltage than the nano-textured samples, since the volume of etched ITO in the former is more than that in the latter. For the same reason, the convex-hybrid-textured samples also have higher forward voltage than the concave-hybrid-textured samples. Under the injection current of 20 mA, the average values of forward voltages of the flat samples, nano-textured samples, concave-hybrid-textured samples, and convex-hybrid-textured samples are measured as 2.96 V, 3.02 V, 3.03 V, and 3.07 V, respectively. It suggests that the surface texturing of the ITO layer would not degrade the electrical properties of LED chips.

Figure 4 shows the functional curves of light-output power versus injection current for these samples. It is shown that the textured ITO surface would enhance the light-output power, compared to the flat ITO surface. This is because of the improvement of the probability of lights entering the escape cone on the textured interface between ITO and air. It is also shown that the hybrid-textured samples lead to more light extraction than the nano-textured samples, and the convex-hybrid-textured samples give the best results. At 20 mA, the average values of light-output power of the flat samples, nano-textured samples, concave-hybrid-textured samples, and convex-hybrid-textured samples are about 28.81 mW, 32.07 mW, 33.35 mW, and 33.97 mW, respectively. Compared to the flat counterparts, these three types of textured samples provide the enhancement of 11.3%, 15.8%, and 17.9%, respectively.

Figure 5 shows the typical values of light-output efficiency under different injection current. The light-output efficiency is defined as the light-output power divided by the electric-input power. It is shown that the light-output efficiency can be improved by ITO surface texturing, and the hybrid-textured samples have superior performance to their nano-textured counterparts. This can also be attributed to the better light-extraction efficiency. The average values of light-output efficiencies of the flat samples, nano-textured samples, concave-hybrid-textured samples, and convex-hybrid-textured samples are estimated to be 48.7%, 53.0%, 55.1%, and 55.3%, respectively, at 20 mA. Compared to the flat counterparts, these three types of textured samples provide the enhancement of 8.8%, 13.1%, and 13.5%, respectively. It is also shown that the light-output efficiency decreases significantly as the injection current increases. The convex-hybrid-textured samples have slightly higher light-output efficiency than concave-hybrid-textured samples only at small injection currents from 10 to 30 mA. On the contrary, the former has less light-output efficiency than the latter at the injection currents from 35 to 100 mA. This indicates that the concave-hybrid-textured pattern is preferred if a large injection current, such as 100 mA, is required.

To further understand the enhancement of light-output induced by ITO texturing, the two-dimensional finite difference time domain (2D FDTD) was used for numerical simulation^[16]. To reduce the computation resource, as shown in Fig. 6, the 2D model only consists of five layers, including a 2 $\mu$m-thick sapphire substrate, a 4.73 $\mu$m-thick n-type GaN, a 0.33 $\mu$m-thick p-type GaN, a 0.23 $\mu$m-thick ITO, and the perfect electrical conductor (PEC) layer below the substrate. The width of the LED chips in the simulation domain was set to be 32 $\mu$m. Since the perfect matched layer (PML) boundaries were used, the width of the chip and the thickness of the substrate can be reduced^[16]. The MQW was simplified as the interface between the two types of GaN, and the electric point dipole was chosen as the source for spontaneous emission. Two orientations of dipole source along the two axes are considered, and three typical locations shown in Fig. 6 were simulated. The nano-pattern was simplified as close-packed triangles with the size of 30 nm (height) $\times$ 200 nm (width), while the concave-pattern and convex-pattern were 51.8 nm (height) $\times$ 3.2 $\mu$m (width) and 51.8 nm (height) $\times$ 2.4 $\mu$m (width), respectively, and the period of the micro-pattern is 6 $\mu$m. At the wavelength of 460 nm, the refractive indices of sapphire, GaN, and ITO are set to be 1.78, 2.45, and 2.0221, respectively. Simulation results show that the nano-pattern, concave-hybrid pattern, and convex-hybrid pattern exhibits the improvements of 14.68%, 25.93%, and 26.32%, respectively, for light-extraction efficiency. The variation trend is consistent with the experimental results, and demonstrates that the light-output can be significantly enhanced by the hybrid-textured ITO surface.

4. Conclusion

GaN-based LED chips with flat, nano-textured, concave hybrid micro/nano-textured, and convex hybrid micro/nano-textured ITO surface had been prepared in a mature product line. The nano-texturing was realized by maskless wet-etching, and the micro-texturing was achieved by standard photolithography and wet-etching. All these techniques are feasible, simple, and low cost. The results show that the textured ITO surface would induce a higher forward voltage, light-output power, and light-output efficiency than the flat ITO surface. Compared to the nano-textured samples, the forward voltage of hybrid-textured samples is slightly raised, while both the light-output power and light-output efficiency are significantly improved. Moreover, the convex-hybrid-textured samples give the highest forward voltage, and provide the best results of light-output power. Under the injection current of 20 mA, compared to the flat samples, the light-output powers of the nano-textured samples, concave-hybrid-textured samples, and convex-hybrid-textured samples are enhanced by 11.3%, 15.8%, and 17.9%, respectively. The 2D-FDTD simulation results are consistent with the experiments. However, considering the light-output efficiency, the convex-hybrid pattern shows better performance under small injection current, while the concave-hybrid pattern is preferred under large injection current. Furthermore, the electrical and optical performance can be improved further if the etching depth is optimized.

Acknowledgement: The authors would like to thank Neo-Neon LED lighting International Ltd. for its help in the experiments.