Fig. 1.
Diagram of the proposed ADC
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| Citation: |
Wenwei He, Qiao Meng, Yi Zhang, Kai Tang. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS[J]. Journal of Semiconductors, 2014, 35(8): 085004. doi: 10.1088/1674-4926/35/8/085004
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W W He, Q Meng, Y Zhang, K Tang. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS[J]. J. Semicond., 2014, 35(8): 085004. doi: 10.1088/1674-4926/35/8/085004.
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A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS
DOI: 10.1088/1674-4926/35/8/085004
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Abstract
A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88×0.88 mm2 with the pad. It consumes 210 mW from a 1.2 V single supply. -
References
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