1. Introduction

Graphene, the two-dimension material first found in 2004^[1], has attracted large numbers of researchers due to its unique properties. The properties such as high mobility^[2], optical transparency^[3] and its single atom layer carbon structure make graphene have great potential in industrial applications and scientific research. Graphene-based functional devices were fabricated within a few years, such as flexible displays^[4], RF devices^[5] and electrodes^[6].

The graphene based field effect transistor (FET) has been a hot topic as a fundamental device of circuit applications. The high mobility and thermal conductance lead this material to be an ideal candidate to replace or complement conventional silicon as the basic material in integrated circuits. However, there are many critical issues needing to be solved in the road to graphene logic devices. Besides band gap opening^[7] and controllable doping of the graphene channel^[8], stability of graphene devices^[9] is also an important challenge for applications of graphene FET. As single layer graphene is an all-surface material, the stability of graphene FET is sensitive to its surface and interface conditions, which depend on the adsorption in the air, the quality of the substrate interface and the processing contamination. Hysteresis behavior, mainly caused by the graphene surface and interface charges, is a typical phenomenon in transfer characteristic curves of graphene FET under natural ambient circumstances. In many studies, hysteretic behavior has been studied under various interfaces (water^[10], polymer^[11], dangling^[12]) and follow-up processes (in the air^[13], under dry oxygen^[14], annealing^[14]). These works show that the hysteretic phenomenon has much dependence on the surface and ambient conditions of graphene FET.

In this work, we studied the affect of the electrical test behavior on the electrical performance of graphene FET. Back gate graphene FET on SiO₂/Si substrate was fabricated and its hysteresis behavior of the drain current versus the gate voltage (the ${I_{\text{d}}}{\text{ - }}{{\text{V}}_{\text{g}}}$) curve was studied. The hysteresis parameters were compared in different back gate sweep ranges, in a repeated test process and under different stress voltages. The interface trapped electrons residual and its accumulation between different test-times were observed during the test, which indicated that the electrical measurement could bring an unrecoverable impact to the electrical performance of graphene FET. The driven-out phenomenon of interface trapped electrons has also been detected under negative gate voltage stress. This work provides a deeper insight into the interface of graphene/SiO₂ and ways to optimize graphene FET electrical performance.

2. Experiments

The studied device is a graphene channel FET, isolated by the dielectric layer of silicon oxide on the N-type silicon substrate. Figure 1(a) shows the structure schematic diagram of the graphene FET. The graphene was synthesized by chemical vapor deposition (CVD) on copper film and then coated with PMMA to support graphene in the following etching and transfer process. The copper substrate was removed by the wet etching process and PMMA/graphene was transferred onto the silicon substrate with 100 nm CVD silicon oxide as the dielectric. After the cleaning of PMMA with an acetone solution, the drain/source (S/D) areas were patterned by optical lithography and followed with thermal evaporation 10 nm Cr and 90 nm Au. With the lift-off process, the S/D metal electrodes were left precisely on the surface of graphene. In order to etch the graphene channel, the second lithography was used with oxygen plasma.

Figure 1(b) shows the optical microscope graph of graphene FET, which indicates that the sample is relatively clean and the S/D metal is well patterned after the lift-off process.

3. Results and discussion

Raman spectrums of both transferred and processed graphene by using the 473 nm laser are shown in Fig. 2. The D peak is insignificant in Fig. 2(a), confirming the integrity of the graphene material after transfer. The inset graph in Fig. 2(a) shows the graphene 2D curve fitted well with a single peak lorentz curve, which confirms the graphene has a single layer^[15]. In Fig. 2(b), the G-peak and 2D-peak shift right to 1593 cm^-1 and 2714 cm^-1, respectively after the processes, which indicates that the graphene channel is highly P-doped^[16]. The channel P-doped property was also observed in the late electrical measurement. The high doping suppressed the intensity of the 2D peak and resulted in the decreasing of ${I_{{\text{2D}}}}/{I_{\text{G}}}$ (from 2.44 in the transferred graphene to 1.03 in the processed graphene).

The electrical characteristic of graphene FET was measured by using an Agilent 4156 semiconductor analyzer at room temperature and in air. Figure 3(a) shows a typical drain current versus the gate voltage (${I_{\text{d}}}{\text{ - }}{{\text{V}}_{\text{g}}}$) sweep curve of the back gate graphene FET. The gate voltage sweeps from -10 to 100 V and then sweeps back to -10 V. Drain and source voltages stay in 0.05 and 0 V. The forth and back sweep curve has a different charge neutral point (corresponding to minimum conductivity), which coincides with the Dirac point of graphene. The drain current and gate voltage in the charge neutral points are defined as ${I_{{\text{dnp}}}}_{\_{\text{Forth}}}$ & ${V_{{\text{np}}\_{\text{Forth}}}}$ in the forth sweep, and ${I_{{\text{dnp}}}}_{\_{\text{Back}}}$ & ${V_{{\text{np}}\_{\text{Back}}}}$ in the back sweep.

As in Fig. 3(a), the charge neutral point voltages are both over 70 V, which indicates the graphene has been highly P-doped, which is also confirmed from the conclusion of the above Raman measurement. The intrinsic P-doping of graphene is mainly caused by the hole doping from the adsorbed water and oxygen molecules^[9] or contamination on the graphene surface^[17]. It is obvious that there is a positive shift of the charge neutral point voltage in the back sweep compared with the forth process. This shift is mainly caused by the electrical screening effect originating from the trapped charges in the graphene/SiO₂ interface^[10]. Figure 3(c) shows the schematic diagram of the screen effect from the interface traps. With the back gate sweeping in positive voltage, electrons in the graphene channel are gradually accumulated into the graphene/SiO₂ interface trap center. The electrons under the graphene partly screen the positive back gate electric field, which results in decreasing the electric potential of the graphene. Consequently, the voltage at the neutral point shifts up to offset the screened electric field.

To study the influence of electrical measurement on graphene FET electrical performance, the relation between neutral point voltage shifts $\Delta {V_{{\text{np}}}}({\text{equals}}\;{\text{to}}\;{V_{{\text{np}}\_{\text{Back}}}} - {V_{{\text{np}}\_{\text{Forth}}}})$ with the gate voltage sweep range was studied, as shown in Fig. 3(b). The $\Delta {V_{{\text{np}}}}$ reaches as 10.7 V / 7.7 V/6 V at 0-100 V / 70-100 V / 80-100 V sweep ranges, respectively. The $\Delta {V_{{\text{np}}}}$ decreases with the reducing of the ${V_{\text{g}}}$ sweep range in the positive domain. The shift decrease is caused by the different density of captured electrons inducing a different screen effect. This phenomenon clearly shows the electrical measurement itself having a significant impact on the test result.

To further understand the impact of the electrical test, the studied device is tested repeatedly under different recovery times (10, 10, 30, 50, 100, 300 and 500 s). The stress module of the Agilent analyzer is taken as the measurement equipment, which keeps the stress voltages at zero and the stress time equaling the recovery time. The extracted neutral point voltage ${V_{{\text{np}}}}$ and its shift $\Delta {V_{{\text{np}}}}$ are shown in Fig. 4(a), where the square and circle curves represent the neutral point voltage in the forth sweep and the back sweep. The ${V_{{\text{np}}}}$ always keep increasing with the repeated test times in both the forth and back sweeps, even after the recovery time of 500 s. It can be explained that the trapped electrons in the graphene/SiO₂ interface have not been released completely at the end of each test. The residual interface electrons, which can stay in traps over 500 s, will continuously accumulate and enhance the electrical field screening effect in the next test process, and ultimately lead to the raising of ${V_{{\text{np}}}}$. The down-triangle curve with the right axis in Fig. 4(a) stands for $\Delta {V_{{\text{np}}}}$ versus different test times, shows $\Delta {V_{{\text{np}}}}$ decreases with the increasing of test times. It is obvious that $\Delta {V_{{\text{np}}}}$ is caused by the difference of the interface charge number, just as:

$ \Delta {V_{{\text{np}}}} \propto {\text{ }}\Delta {Q_{{\text{it}}}} = {Q_{{\text{itB}}}} - {Q_{{\text{itF}}}}, $

(1)

where ${Q_{{\text{itB}}}}$ and ${Q_{{\text{itF }}}}$ are the interface trapped charge under back and forth sweep respectively, and $\Delta {Q_{{\text{it}}}}$ is the difference of trapped charges. Due to the limitation of interface trap sites, the gap of the trapped charge number between the forth and back sweeps shrinks with the increasing of residual interface electrons. Therefore, the voltage shift decreases with the growth of test times.

The drain current in neutral point ${I_{{\text{dnp}}}}$ and its shift $\Delta {I_{{\text{dnp}}}}$ have the same trend as the voltage, shown in Fig. 4(b). The ${I_{{\text{dnp}}}}$ in the forth and back sweep, which is shown as the square and circle curves, has direct proportion with the test times. Nevertheless, the current shift $\Delta {I_{{\text{dnp}}}}$ decreases with the repeated test times, shown as the down-triangle curve with the right axis in Fig. 4(b). A comparison of Fig. 4(a) with Fig. 4(b) illustrates that there are many similarities of the test times dependency relationship for neutral voltage and neutral drain current. The similar trend of neutral voltage and neutral drain current may be caused by the charge injection in the electrons trap/de-trap process^[18]. The specific mechanism of the similarity needs further research.

The effect of gate voltage stress on graphene FET is depicted in Fig. 5. The studied devices are continuously under the gate stress voltage ranging from 20 to -40 V, the ${I_{\text{d}}}$ -${V_{\text{g}}}$ results are tested at the time of 0, 10, 20, 50 and 100 s, repeatedly. Figure 5 shows the relative change of ${V_{{\text{np}}}}$ in both forth and back sweeps. To eliminate the variation of electrical characteristics between the different test samples, all the neutral point voltages are modified into a relative value (divided by corresponding primary ${V_{{\text{np}}}}$ at the time of 0 s, ${V_{{\text{np}}\_{\text{Forth0}}}}\;{\text{or}}\;{{\text{V}}_{{\text{np}}\_{\text{Back0}}}})$. Figure 5(a) shows the relative ${V_{{\text{np}}}}$ change with the stress time in the forth sweep process and in Fig. 5(b) the back sweep process. The relative neutral point voltages are greater than 1, which indicates the ${V_{{\text{np}}}}$ in the forth sweep is shifted up, compared with the primary neutral point voltage. With the gate stress voltage reducing from 20 to -40 V, the relative ${V_{{\text{np}}}}$ has a significant decrease, especially in the stress of -40 V. This result denotes that when the gate stress voltage is negative, the interface trapped electrons are partly driven out under the stress period, and ultimately results in the suppression of the screen effect of interface trapped electrons (and vice versa for the positive stress voltage).

4. Conclusion

In summary, the studied graphene FET has initially been P-doped in the air by the absorption of water molecules or process contamination. For the P-type graphene FET, the interface trapped electrons (caused by the positive gate sweep voltage) partly screen the gate electrical field, which results in the neutral point voltage shift of graphene FET. The shift $\Delta {V_{{\text{np}}}}$ is inversely proportional to the positive ${V_{\text{g}}}$ sweep range, which indicates the test result has a strong dependence on the electrical measurement method. In the repeated test experiment, the continuous increasing of ${V_{{\text{np}}}}$ with test times shows the interface screen electrons have residual and can accumulate at the end of each test. The gate voltage stress experiment proves that the negative gate voltage stress has a significant impact on the driving out of the trapped electrons at the interface of graphene/SiO₂, which results in the significant decreasing of neutral point voltage with the reducing of stress voltage.