1. Introduction

Strain engineering has been developed as a key technology to improve the performance of Si-based devices without scaling their dimensions^{[1, 2, 3]}. As one of the widely used methods to form strained silicon (sSi) devices, stress liner technology, which is based on a contact etch stop layer (CESL), has attracted much attention^{[4, 5]}. It is widely accepted that NMOS needs a tensile CESL (t-CESL) to form a tensile channel and PMOS needs a compressive CESL (c-CESL) to form a compressive channel^{[5, 6]}. To enhance the performances of NMOS and PMOS simultaneously, dual stress liner (DSL) technology has been developed^{[6, 7, 8, 9]}. However, it is complicated to fabricate t- and c-CESL on the same wafer. If NMOS and PMOS can be improved by the same type of CESL, the fabrication processes will be effectively simplified.

Our previous work demonstrated that a well designed trench structure formed in a strained PMOS can change the stress state of the channel, and thus significantly improve the device performance^{[10, 11]}. In this paper, the applicability of the trench structure in strained NMOSFET is investigated using numerical simulation. It is demonstrated that, with such a structure, the performance of NMOS can be enhanced by a c-CESL. This approach provides an alternative to enhance NMOS performance besides the traditional t-CESL technology.

2. Device structure

Figure 1 is the schematic cross-section view of the c-CESL strained NMOS with a trench-based structure. Unlike the conventional shallow isolation trench (STI) filled with SiO$_{2}$, the trench here is covered by a thin layer of c-CESL. With this structure, the channel of the device is tensile-strained, whereas in the conventional strained device with the same c-CESL, the channel is compressive-strained. The mechanical equilibrium is crucial to explain the effects of the trench-based structure on channel stress. A detailed discussion will be provided later.

The simulation work is conducted using the Sentaurus process to investigate the effects of the trench structure on device performance. For comparison, the trench-based, conventional strained and unstrained devices are all simulated. Their geometric parameters are almost the same. Their gate-length and gate-thickness are set to be 95 and 36 nm, respectively. The thicknesses of the gate oxide and spacer are 4 and 32.5 nm, respectively. The length of the source/drain region is 150 nm. The concentration of dopants in the source/drain region is 1 $\times$ 10$^{20}$ cm$^{-3}$. The doping concentrations in the channel and the lightly doped drain (LDD) are 1 $\times$ 10$^{18}$ and 1 $\times$ 10$^{19}$~cm$^{-3}$, respectively. Each strained device is covered by a 120-nm-thick c-CESL with a stress of -2.5 GPa. The trench-width and trench-depth are 800 nm and 700 nm, respectively.

3. Results and discussion

3.1 Stress modulation mechanism

Figures 2(a) and 2(b) show the distribution of the longitudinal component of the stress tensor $\sigma_{xx}$ in the trench-based and the conventional strained devices, respectively. As expected, it is observed in Figure 2(a) that the conventional strained device has a compressive channel. But this is not the case for the trench-based device demonstrated in Figure 2(b), which has a tensile channel instead.

For clarity, the longitudinal distribution of, $\sigma _{xx}$ in the channel (at a depth of 1 nm beneath the Si surface) is demonstrated in Figure 3. It is shown that the states of stress in the two strained devices are opposite. For the conventional device, the average $\sigma _{xx}$ in the channel is negative ($-333$ MPa). For the trench-based device, however, the average $\sigma _{xx}$ in the channel is positive (256 MPa). The results indicate that the trench-based structure can transform the compressive-strained channel into a tensile-strained one.

To investigate the mechanism of the stress modulation effect illustrated in Figures 2 and 3, the method presented in Reference~^[5] is employed in this work. As shown in Figure 4, the CESL layer of the trench-based device is split into the following four CESL zones for convenience:

(1) top-CESL, the CESL above the gate region;

(2) lateral-CESL, the CESL above the spacer region;

(3) bottom-CESL, the CESL above source and drain region;

(4) trench-CESL, the CESL in the trench structure.

The effect of each CESL zone on channel stress is simulated by keeping the whole CESL but exerting $-2.5$ GPa of intrinsic stress only in one CESL zone (the others are stress free). The contribution of each strained CESL zone to $\sigma _{xx}$ in the device is shown in Figure 5.

Figure 6 shows the contributions of the strained top-, lateral-, bottom-, and trench-CESL to the stress in the channel, respectively. In agreement with Reference ^[5], the effects of the top- and bottom-CESL on channel stress are opposite. However, due to the different device structures, there is a significant difference between the results of this work and Reference~^[5]. In the trench-based device, the top-CESL dominates the channel stress, whereas in the conventional device discussed in Reference~^[5], the bottom-CESL plays the most important role. In the conventional strained device, the bottom-CESL has a large lateral expansion and covers the source/drain and STI regions. Through the materials in such regions, the stress induced by the bottom-CESL can be transmitted to the channel. As discussed in Reference~^[5], the bottom-CESL gains the advantage in the competition with the top-CESL. In other words, the compressive channel stress induced by the bottom-CESL overwhelms the tensile one induced by the top-CESL. Therefore, a compressive channel is achieved. In the trench-based device, however, the lateral expansion of the bottom-CESL is limited by the trench structure. Thus, as shown in our simulation results, its effects on channel stress are significantly weakened. Then the top-CESL becomes dominant in its competition with the bottom-CESL. Taking the stress at the middle point of the channel as an illustration, it is observed from Figure 6 that the contributions of the top- and bottom-CESL to the channel stress are 281.2 and $-6.3$ MPa, respectively. Therefore, the channel stress becomes tensile.

3.2 Electrical performance

To investigate the effect of the trench structure on device performance, the electrical characteristics of the trench-based strained device, the conventional strained device and unstrained devices are simulated. The resulting output and transfer curves are shown in Figures 7 and 8 respectively.

As illustrated in Figure 7, the drain current of the conventional strained device is 18.4 % lower than that of the unstrained device at the bias of $V_{\rm gs}$ $=$ 2 V and $V_{\rm ds}$ $=$ 2 V. It is also observed that the corresponding drain current of the trench-based device is 22.2 % larger than that of the unstrained device. The difference in device performance results from the different channel stress states. The poor performance of the conventional strained device is due to the suppression of the electron mobility caused by the compressive stress in the channel. On the other hand, the improved performance of the trench-based device is a reflection of the enhanced electron mobility due to the tensile channel.

Figure 8 shows the transfer characteristics of the three devices. It is observed that, at the bias of $V_{\rm gs}$ $=$ 2 V and $V_{\rm ds}$ $=$ 2 V, the transconductance of the trench-based device is 22.4 % larger than that of the unstrained device, whereas the conventional strained device's transconductance is 23.9 % lower. These results confirm the idea that the application of a trench-based structure can improve the electrical performance of strained NOSFET.

4. Conclusion

A trench-based structure to modulate the stress in strained NMOSFET is reported. With this structure, NMOSFET can be enhanced by a c-CESL. The effects of this structure on the device's characteristics are investigated by numerical simulation using the SENTAURUS PROCESS. It is demonstrated that, when a $-2.5$ GPa c-CESL is deposited on the device's surface, the application of this structure successfully transforms the average $\sigma_{xx}$ in the channel from negative ($-333$ MPa) into positive (256 MPa), which contributes to a significant improvement of the device's $I$-$V$ characteristics. While being applied in strained CMOS, this technology offers a solution to enhance N- and P-MOS by the same type of CESL, and thus provides a potential alternative besides the DSL technology.