J. Semicond. > 2015, Volume 36 > Issue 10 > 105003
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SEMICONDUCTOR INTEGRATED CIRCUITS

A CMOS frontend chip for implantable neural recording with wide voltage supply range

Jialin Liu1, 2, Xu Zhang1, Xiaohui Hu1, Yatao Guo2, Peng Li1, Ming Liu1, Bin Li2 and Hongda Chen1

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DOI: 10.1088/1674-4926/36/10/105003

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Abstract: A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper.The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC).The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a-3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device.A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain.The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz.The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s.The measured effective number of bits (ENOB) of the ADC is 8.7 bits.The entire circuit draws 165 to 216 μ<A current from the supply voltage varied from 1.34 to 3.3 V.The prototype chip is fabricated in the 0.18-m CMOS process and occupies an area of 1.23 mm2 (including pads).In-vitro recording was successfully carried out by the proposed frontend chip.

Key words: neural amplifier, instrumental amplifier, cyclic analog-to-digital converter, neural recording system, wide voltage supply range



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Fig. 1.  Architecture of the neural recording front-end chip.

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Fig. 2.  Simplified schematic of the fully differential preamplifier.

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Fig. 3.  Specific schematic of OTA1 used in the preamplifier.

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Fig. 4.  The variation of two different OTAs (with fixed bias voltage and supply-proportional bias voltage) under different supply voltages.

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Fig. 5.  AC-response of the amplifier (preamplifier and IA) under different supply voltage.

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Fig. 6.  (a) Simplified schematic of dual-amplifier IA. (b) Specific schematic of OTA2.

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Fig. 7.  Architecture of the adopted cyclic ADC.

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Fig. 8.  Sequence diagram of the cyclic ADC in one sampling period.

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Fig. 9.  Microphotograph of the proposed chip.

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Fig. 10.  Measured frequency response under different supply voltage.

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Fig. 11.  Measured input-referred voltage noise spectra of the frontend amplifier (including preamplifier and IA).

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Fig. 12.  Power spectral density of the cyclic ADC with input of 1kHz sinusoidal signal.

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Fig. 13.  Measured ENOBs of the cyclic ADC under different supply voltages.

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Fig. 14.  In-vitro experiment. (a) Whole testing system. (b) Recorded spikes train (digital outputs).

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Table 1.   Experimental characteristics and comparison.

Parameter Reference [19]Reference [20]Reference [21]This work
Technology ($\mu$m)0.350.130.180.18
Chip area (mm$^2)$1.51254.411.23
Supply voltage (V)3.31.21.81.3-3.3
Passband (Hz)100-70001-100 (280-10000)350-117001-5700
Input-referred noise ($\mu$V$_{\rm rms} )$6.85214 (2.2)11.26.7104
Gain (dB)7740/5649-6646
Sampling rate (kS/S)--31.25125130
ADC ENOB--9.727.658.7
Fully differentialNoYesNoYes
Channel196321
Power/channel (mW)1.47860.0650.1210.22-0.71
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    Received: 19 March 2015 Revised: Online: Published: 01 October 2015

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      Article Navigation >  Journal of Semiconductors  > 2015  >  36(10): 105003
      Jialin Liu, Xu Zhang, Xiaohui Hu, Yatao Guo, Peng Li, Ming Liu, Bin Li, Hongda Chen. A CMOS frontend chip for implantable neural recording with wide voltage supply range[J]. Journal of Semiconductors, 2015, 36(10): 105003. doi: 10.1088/1674-4926/36/10/105003 ****J L Liu, X Zhang, X H Hu, Y T Guo, P Li, M Liu, B Li, H D Chen. A CMOS frontend chip for implantable neural recording with wide voltage supply range[J]. J. Semicond., 2015, 36(10): 105003. doi: 10.1088/1674-4926/36/10/105003.
      Citation:
      Jialin Liu, Xu Zhang, Xiaohui Hu, Yatao Guo, Peng Li, Ming Liu, Bin Li, Hongda Chen. A CMOS frontend chip for implantable neural recording with wide voltage supply range[J]. Journal of Semiconductors, 2015, 36(10): 105003. doi: 10.1088/1674-4926/36/10/105003 ****
      J L Liu, X Zhang, X H Hu, Y T Guo, P Li, M Liu, B Li, H D Chen. A CMOS frontend chip for implantable neural recording with wide voltage supply range[J]. J. Semicond., 2015, 36(10): 105003. doi: 10.1088/1674-4926/36/10/105003.
      shu

      A CMOS frontend chip for implantable neural recording with wide voltage supply range

      DOI: 10.1088/1674-4926/36/10/105003
      • 1.

        State Key Laboratory on Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

      • 2.

        School of Electronic and Information Engineering, South China University of Technology, Guangzhou 510000, China

      Funds:

      Project supported by the National Natural Science Foundation of China (Nos.61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No.KJZD-EW-L11-01).

      • Received Date: 2015-03-19
      • Accepted Date: 2015-04-29
      • Published Date: 2015-01-25

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