1. Introduction

Single event upset (SEU) hardening has become more complex due to the shrinking of device sizes and the increase in circuit density. Conventional hardened-by-design (HBD) techniques to mitigate soft errors,such as triple modular redundancy (TMR) or dual inter locked cell (DICE),are based on redundancy,requiring that an incident single-event (SE) ion affects only one circuit node. However,such designs are vulnerable to ion hits that result in multiple nodes collecting charge,as shown by Olson et al.^[1] and Amusan et al.^[2]. For deep sub-micron technologies,the proximity of circuit nodes may result in charge collection at multiple nodes from a single ion strike^{[3, 4]}.

One hardened-by-design technique to help mitigate multiple node collection is guard contacts^{[5, 6, 7]}. The use of well contacts and a guard ring is effective in mitigating parasitic PNP bipolar effects^[6],but it is limited to the struck devices only. Guard and well contacts are used to help mitigate bipolar conduction by stabilizing well potential during a single event effect (SEE)^{[6, 7]},but they are only useful for reducing multi-node charge collection effects associated with NMOS sensitive node pairs or PMOS sensitive node pairs in the same single well.

Another hardened-by-design technique to help mitigate multiple node collection is the 2-interleaving storage element^{[8, 9]}. The technique of the 2-interleaving storage element is only effective in separating NMOS sensitive node pairs or PMOS sensitive node pairs,which cannot separate the NMOS or PMOS node pairs.

In this paper,three-dimensional (3-D) technology computer aided design (TCAD) simulation shows that the most vulnerable node pairs of a DICE SRAM cell are the PMOS-NMOS sensitive node pairs in different wells other than the NMOS sensitive node pairs or PMOS sensitive node pairs in the same single well. Then a 4-interleaving cell of dual DICE is designed as an effective method to separate all the sensitive node pairs in an area-efficient manner. The 3D TCAD simulation and the radiation experiment both show that the new 4-interleaving cell of dual DICE significantly improve soft error resilience compared to the reference SRAM DICE cell.

2. Sensitive node pairs in DICE cell

The DICE is a storage element that relies on dual redundancy of internal circuit nodes to achieve soft-error resilience [Calin 96]. A DICE storage element is immune to single event upsets affecting single circuit nodes,but is vulnerable to single event multiple upsets affecting multiple circuit nodes [Baze 08]. The basic 12-transistor DICE storage element is shown in Figure1.

When the drain contact node of an "off" transistor in the DICE design,e.g.,the drain contact node n1 in Figure1,is hit by a particle,the circuit node connected to this drain contact node,e.g.,circuit node A,can temporarily switch its logic state. This can turn off a previously ``on'' transistor,e.g.,M7,and turn on a previously "off" transistor,e.g.,M4,causing the following behaviors in the remaining circuit nodes:

(1) Circuit node B is now driven by both "on" transistors M3 and M4. This results in voltage contention at circuit node B.

(2) The change in the voltage of circuit node B reduces the current drive of M6. As a result,node C is now weakly driven by M6. (3) Circuit node D is now left floating (M7 and M8 are "off").

If no other circuit node in the DICE storage element is affected by the single event,circuit node A will eventually recover its original state,and the storage element will continue to produce correct outputs. However,if an additional drain contact node of an "off" transistor is hit by the same single event,an upset may be induced in the storage element.

Recent studies have shown that bipolar amplification between PMOS sensitive node pairs due to the n-well potential collapse and charge diffusion between sensitive node pairs in the case of a single strike are the main charge sharing mechanisms^{[4, 10]}. Dodd et al. have shown that parasitic bipolar conduction may induce multiple node collection between PMOS-NMOS transistors. Considering all the charge collection mechanisms,the sensitive node pairs in a DICE cell at different initial states are shown in Table1.

3. The proposed 4-interleaving cell of dual DICE design

Due to shrinking device sizes,the sensitive node pairs in a traditional DICE cell are so close to each other that the traditional DICE cell is more sensitive to SEU. As we discussed in Section 2,the distances between most of the sensitive node pairs in a traditional DICE cell are less than 1 $\mu$m. Especially,the sensitive NMOS--PMOS node pairs are (n5,n4),(n3,n2) and (n7,n6). At the same time,a different sensitive node pair of the DICE cell has a different upset mechanism,so single event upset hardening has become more complex for the DICE cell.

In this paper,a 4-interleaving cell of a dual DICE layout technique is proposed to reduce susceptibility to upsets for DICE elements in 65 nm technology. Figure2 shows a traditional DICE cell layout. First,we divide the traditional DICE layout into four parts,and make a copy to have two of the same DICE layouts: DICE1 and DICE2. Here we make the DICE1 cell the target cell. For each sensitive node pair in DICE1 layout that can be simultaneously ``affected'' by a single event,we place parts of another DICE layout (DICE2) between the sensitive node pair of DICE1.

Figure3 shows the 4-interleaving implementation of dual DICE implementation for the dual DICE storage element. Table1 shows the distances of all the sensitive node pairs in the traditional DICE layout and in the 4-interleaving cell layout of dual DICE. We can see that 4-interleaving cell layout of dual DICE hardened design method effectively separate all the sensitive node pairs,and effectively increase the distances of all the sensitive node pairs in DICE1.

4. Radiation simulation result

Accurate single event simulations can provide effective quantitative assessment of a 4-interleaving cell layout of dual DICE hardened design. We have used the tool Cogenda^[11] which accurately simulates single event charge distribution and charge collection while fully accounting for layout,substrate,and circuit details. This single event simulation tool provides accuracy similar to a full 3D TCAD device simulation,and is fast enough to run a very large number of single event experiments as required for cross-section and LET threshold prediction.

To evaluate the dual DICE 4-interleaving storage element layout and compare it to the traditional DICE cell layout,we implemented two layouts in 65 nm CMOS technology for the basic DICE circuit (Figure1),traditional DICE cell layout (Figure2) and the dual DICE 4-interleaving storage element layout (Figure3). Note that both layouts use exactly the same device sizing. Figure4 shows the 3D model of the simulated dual DICE 4-interleaving storage element.

As shown in Figure5,the lowest LET upset threshold for 4-interleaving cell layout of dual DICE is almost an order of magnitude larger than the lowest LET upset threshold for DICE. These simulation results also indicate that the sensitive NMOS--PMOS node pairs: n2--n3,n4--n5 and n6--n7 are the most vulnerable sensitive node pairs in both the traditional DICE cell and the 4-interleaving cell layout of dual DICE.

While the simulations presented here are relatively limited in scope,they show the effectiveness of the dual DICE 4-interleaving layout hardened design method and quantify the reduction in LET upset threshold for the 4-interleaving cell layout of dual DICE compared to the traditional DICE.

5. Test chip implementation and radiation experiment result

To evaluate the effectiveness of the 4-interleaving cell layout of dual DICE,we implemented two 128 kb SRAM circuits,with the traditional DICE and the 4-interleaving cell layout of dual DICE respectively to be the SRAM cells,in 65-nm CMOS technology. The layout of it is shown in Figure6.

Radiation experiment test conditions for the two SRAM circuits are exactly the same: the test mode is 55H,the circuit's array power is 1.2 V. All the heavy ions are at an angle of incidence tilt $=$ 0$^\circ$,azimuth $=$ 0$^\circ$. The heavy ion results of the two 128 kb SRAMs,with the traditional DICE and the 4-interleaving cell layout of dual DICE,respectively to be the SRAM cells,are summarized in Table2.

The radiation experiment result shows that the dual DICE 4-interleaving SRAM have no upset with both F and Cl to be the incident ion. The LETth of the dual DICE 4-interleaving SRAM is more than 20 MeV$\cdot$cm$^{2}$/mg; while we can see the traditional DICE SRAM upsets with F to be the incident ion,so the LETth of the traditional DICE SRAM is less than 5~MeV$\cdot$cm$^{2}$/mg. As shown in Table2,the SEU cross section per bit for the traditional DICE SRAM is almost two orders of magnitude larger than SEU cross section per bit for the 2-DICE interleaving SRAM. The results of the heavy-ion testing generally support the simulation results.

The SEU response of the two different cell layouts suggests that the 4-interleaving cell of the dual DICE layout technique is effective to reduce susceptibility to upsets for DICE elements. By interleaving dual DICE cells,the separation of sensitive nodes can be accomplished without the arbitrary wasting of area to space the nodes sufficiently apart.

6. Conclusion

3D TCAD simulations are used to reveal that the sensitive PMOS--NMOS node pairs in different wells has become the most vulnerable sensitive node pairs,with both in a traditional DICE layout.

In this paper,a dual-DICE design is proposed,which interleaves 4 parts of two DICE storage cells to make them more resistant to multiple node upsets caused by a single event. The technique involves the 4-interleaving of dual DICE cells at a layout level to meet the required spacing between sensitive nodes in an area-efficient manner. By interleaving dual DICE cells,the separation of sensitive nodes can be accomplished without the arbitrary wasting of area to space the nodes sufficiently apart.

The dual DICE 4-interleaving layout hardened design enables the design of the 4-interleaving cell layout of dual DICE with significantly improved soft error resilience compared to our reference traditional DICE SRAM cell. The 4-interleaving cell layout of dual DICE retains the circuit design of DICE,but uses a new layout design. The radiation experiment results using 65nm test circuits demonstrate that the SEU cross section per bit for our dual DICE 4-interleaving SRAM is almost two orders of magnitude less than our reference traditional DICE SRAM. This improvement comes at a negligible power and performance cost compared to DICE,and the 4-interleaving cell layout of dual DICE is a 2 bits storage element,so the area cost is acceptable.