1. Introduction

In recent years, there has been an increasing demand for MMICs in the high millimeter/THz-wave frequency regime^[1]. They are of great interest for high-resolution imaging at the atmospheric windows (94, 140, and 220 GHz), next generation automotive collision avoidance radars (140 GHz), environmental sensors (118/183 GHz), security detection of concealed weapons or explosives (220 GHz), broadband satellite communications and low noise detectors^{[1, 2]}. Due to the high carrier density and superior electron mobility and velocity in the high InAs mole fraction InGaAs channel, InP-based pseudomorphic high electron mobility transistors (PHEMTs) have demonstrated high frequency, low noise, high gain and low power consumption performance. Therefore, the devices are considered to be a unique candidate for those applications. Many high performance InP-based PHEMTs have been reported^{[3, 4, 5]}. For example, an excellent maximum current gain cut-off frequency ($f_{\rm t})$ of 0.6 THz, a maximum oscillation frequency ($f_{\rm max})$ of 1.2~THz, and a maximum extrinsic transconductance ($g_{\rm m, max})$ of 2400 mS/mm for 30 nm InP-based PHEMTs have been fabricated by the Northrop Grumman Corporation^[5].

Excellent performance can be obtained by the combination of gate size scaling, parasitics reduction, and an increase of the InAs mole fraction in the channel that improves electron transport properties. However, with the In-content increased, the impact ionization effects will become serious due to the decreased energy band gap $E_{\rm G}$, which have a number of negative consequences, such as reduced breakdown voltages, an increase in output conductance and Kink effects, and permanent device degradation^[6]. A method of increasing the effective energy band gap $E_{\rm G, eff}$ in the channel is to introduce energy quantization by reducing the channel thickness to dimensions comparable to the electron wavelength, which is shown in Figure 1^{[6, 7]}.

In this paper, the InAs mole fraction has been increased to 0.6, the thickness of the channel was reduced to 11~nm for channel quantization, and the gate-length was reduced to 90~nm. The device structure, device fabrication, DC/RF characteristics and the small-signal model of this device were described. They exhibit the RF characteristics of $f_{\rm t}$ $=$ 180~GHz and $f_{\rm max}$ $=$ 264 GHz. Excellent DC characteristics were also demonstrated with a maximum saturation current density of 755~mA/mm and a $g_{\rm m, max}$ of 1006 mS/mm. The small-signal model from 0.5 to 110 GHz was also established; the $S$-parameters of the model are consistent with those measured from 0.5 to 110~GHz.

2. Device epitaxial structure

The epitaxial wafers were grown by molecular beam epitaxy (MBE) on 3-inch semi-insulating InP (100) substrates. As shown in Figure 2 and Table 1, the layer structure consists of a 15-nm thick n$^{+}$ InGaAs cap (6 $\times$ 10$^{18}$ cm$^{-3})$ for enhanced ohmic contacts, a 14-nm thick undoped In$_{0.52}$Al$_{0.48}$As as the Schottky barrier, an unstrained 3-nm thick undoped In$_{0.52}$Al$_{0.48}$As spacer layer for keeping the two dimensional electron gas (2DEG) far away from the donor impurity, an 11-nm thick quantized and strained In$_{0.6}$Ga$_{0.4}$As channel for superior electron transport properties, and a 400-nm thick undoped In$_{0.52}$Al$_{0.48}$As for protecting the active layers from the potential impurities coming from the SI InP substrate. A Si $\delta$-doping (5 $\times$ 10$^{12}$ cm$^{-2})$ was inserted in the Schottky layer to supply electrons for current conduction.

A typical room temperature Hall mobility of 10000~cm$^{2}$/(V$\cdot$s) and a Hall sheet carrier concentration charge of 3~$\times$ 10$^{12}$ cm$^{-2}$ were measured on undoped-cap layer-calibration samples by the Hall test. The InAs mole fraction of 0.65 and 1 with an electron mobility of 11000~cm$^{2}$/(V$\cdot$s)^[8] and 15000~cm$^{2}$/(V$\cdot$s)^[5] }$ at room temperature have been reported by TRW and the Northrop Grumman Corporation, respectively.

3. Device fabrication

As shown in Figure 2, the gate electrode is located at an offset position from the center toward the source. The structural improvement of the offset gate due to a reduction in the distance between the source and the gate enhances the cut-off frequency ($f_{\rm t})$ and the maximum stable gain (MSG) by minimizing the gate-to-drain capacitance ($C_{\rm gd})$, as well as the source resistance ($R_{\rm s})$. In this device, the space of the source-drain and the space of the source-gate were 2.5 and 0.75 $\mu$m, respectively.

The PHEMTs fabrication were based on both optical and electron beam lithography (EBL). Firstly, the transistor mesa was chemically wet etched to provide isolated active areas by removing a $\sim$200 nm thickness to expose the buffer layer. Secondly, source and drain ohmic contact were spaced 2.5~$\mu$m apart by a lift-off process, followed by the formation of ohmic contacts by using the thermal evaporation of NiGeAu layers and rapid thermal annealing. The contact resistance ($R_{\rm c})$ of 0.045 $\Omega$$\cdot$mm and the specific contact resistivity of 2.3~$\times$~10$^{-7}$~$\Omega$/cm$^{2}$ were obtained by using the transmission line method (TLM). Thirdly, in order to measure on-wafer DC and RF characteristics, the CPW bond pads were formed and connection wires were evaporated.

The most important process was the gate fabrication, which included gate lithography, recess, and metallization. The active devices feature T-shaped Ti-Pt-Au gates, which were defined by electron beam lithography in a three-layer resist (PMMA) process. At first, three layers of electron beam resist of PMMA/A1/UVIII were coated on the surface, then electron beam lithography (EBL) was carried out in turn. Secondly, the gate recess was etched using a succinic acid based solution till the InAlAs barrier layer. Finally, a Ti-Pt-Au gate metal was evaporated and lifted off. The SEM photograph of the fabricated 90-nm T-gate by EBL is shown in Figure 3.

At last, the devices were passivated with 200-nm plasma enhanced chemical vapor deposited (PECVD) Si$_{3}$N$_{4}$ for good reliability, robustness, low leakage current and high breakdown voltage. However, the passivation layer will weaken the RF performance. So the thickness of Si$_{3}$N$_{4}$ should be optimized for a trade-off between DC and RF performance. A detailed view of the device is shown in Figure 4.

4. Device performances and small signal modeling

The fabricated 2 $\times$ 30 $\mu$m InP-based PHEMTs were characterized by measuring the DC and RF performances.

4.1 DC characteristics

The DC characteristics were measured by an Agilent B1500A semiconductor parameter analyzer.

Figure 5 shows the characteristics of drain current ($I_{\rm ds})$ versus drain-source voltage ($V_{\rm ds})$ with various gate-source voltages ($V_{\rm gs})$ of the 90-nm In$_{0.6}$Ga$_{0.4}$As PHEMT device at room temperature. The gate-source voltage ($V_{\rm gs})$ increased from $-0.6$ (bottom) to 0.4 V (top) by a step of 0.2 V. It can be seen from Figure 5 that the PHEMTs exhibited good pinch-off characteristics and saturation drain current. This PHEMTs device can be well pinched off with a threshold voltage ($V_{\rm th})$ of $-0.6$ V.

Figure 6 shows the characteristics of the transconductance ($g_{\rm m})$ and the drain current ($I_{\rm ds})$ versus $V_{\rm gs}$ at $V_{\rm ds}$ of 1.5 V. The maximum $g_{\rm m}$ peak of the device at a $V_{\rm ds}$ of 1.5~V and a $V_{\rm gs}$ of $-0.1$ V was 1006 mS/mm. This high transconductance is due to the superior electron transport properties in the In$_{0.6}$Ga$_{0.4}$As channel and the low ohmic contact resistance. A high drain current density of 755 mA/mm was observed at a $V_{\rm gs}$ of 0.6 V.

The off-state breakdown voltage (BV$_{\rm off-state})$ defined at a gate current of 1 mA/mm is 5.3 V, which benefited from the 200-nm thick Si$_{3}$N$_{4}$ passivation layer and quantized channel. So the gate leakage current was very small, which was crucial for the lower frequency LNA applications since the gate current was a contributing component to shot noise^[8].

4.2 RF characteristics

The RF measurements were performed by using an Anritsu MS4647A series vector network analyzer and an Anritsu 3743A MMW module (70 kHz-110 GHz) at room temperature. The line-reflect-match (LRM) calibration was used to calibrate the measurement system, and the measurements were carried out over the frequency from 0.5 to 110 GHz with a step of 0.1~GHz.

As shown in Figure 7, a $S_{21}$ gain ($\sim$3 dB) was obtained at the millimeter-wave frequency of 110 GHz; the measured $h_{21}$ gain, MAG/MSG, and the stability factor $k$ versus the frequency are also shown in Figure 7. The current gain ($H_{21})$ decreases roughly with a $-20$ dB/decade slope as the frequency increases, so the value of the $f_{\rm t}$ $=$ 180 GHz was obtained by extrapolating $H_{21}$ to 0 dB with the same slope. However, power gain MSG and MAG are related to the stability factor $k$ of the device: when $k$ $<$ 1, the maximum gain is MSG, which decreased with a slope of -10 dB/decade; when $k$ $>$ 1, the maximum gain is MAG, which decreased with a slope of $-20$~dB/decade.

As shown in Figure 7, the inflection point ($k$ $=$ 1) frequency was measured to be 83 GHz, and MAG ($\sim$7.6 dB) was obtained at 110 GHz, so the value of the $f_{\rm max}$ $=$ 264 GHz was obtained by extrapolating MAG to 0 dB with a slope of -20~dB/decade.

At present, due to the instrumentation limit, most of the InP-based HEMTs were measured over the frequency 0-26~GHz or 0-40 GHz^{[9, 10, 11, 12]}, however, the inflection point was usually beyond 40 GHz. Thus, our extrapolated $f_{\rm max}$ was much more accurate than those without a measured inflection point^{[9, 10, 11, 12]}. To the best of the authors' knowledge, this is the first time an inflection point frequency of 83 GHz has been obtained in domestic circumstances.

Excellent DC performances and good RF performances are shown in Table 2 compared with those published InP HEMTs with a similar gate-length.

4.3 Small-signal model of InP-based PHEMTs

From the high frequency measurement up to 110 GHz, the small-signal equivalent circuit for a 2 $\times$ 30 $\mu$m gate width device was deduced. The 18-element model was used to describe the transistor parasitic and intrinsic parameters, which is shown in Figure 8.

The equivalent circuit is commonly shared into an intrinsic section ($g_{\rm m}$, $t$, $g_{\rm ds}$, $C_{\rm gs}$, $C_{\rm ds}$, $C_{\rm gd}$, $R_{\rm i}$, $R_{\rm gd})$, whose elements are bias dependent, and an extrinsic section ($C_{\rm pg}$, $C_{\rm pgs}$, $C_{\rm pd}$, $C_{\rm pgd}$, $L_{\rm S}$, $L_{\rm d}$, $L_{\rm g}$, $R_{\rm s}$, $R_{\rm d}$, $R_{\rm g})$, whose values are extracted during pad de-embedding and assumed to be bias independent^[15].

The model parameters extractions were based on a test structure (PADs) $S$-parameter, and the cold-FET procedure. Firstly, the PAD capacitances were determined by measuring an open structure that consisted of only the PADs; secondly, the parasitic inductance and resistance were determined by the short structure and cold-FET procedure; finally, the intrinsic parameters were extracted after subtracting the parasitic part. The obtained results are listed in Table 3.

It can be noted that $R_{\rm g}$ describes gate line losses, whereas $R_{\rm s}$ and $R_{\rm d}$ commonly describe ohmic contacts quality and access areas. The ratio $R_{\rm d}$/$R_{\rm s}$ of 1.5 is obtained from a small-signal parameter extraction process. This is in agreement with the $R_{\rm d}$/$R_{\rm s}$ ratio of 1.8 obtained from the following formula based on the topology of the transistor:

$R_{\rm s}=(R_{\rm c}/W_{\rm g})+(R_{\rm sh} L_{\rm gs}/W_{\rm g}),$

(1)

$R_{\rm d}=(R_{\rm c}/W_{\rm g})+(R_{\rm sh} L_{\rm gd}/W_{\rm g}).$

(2)

$R_{\rm c}$ and $R_{\rm sh}$ are the contact resistance and channel sheet resistance, respectively, whereas $L_{\rm gs}$ and $L_{\rm gd}$ refer to gate-source and gate-drain spacing distances, respectively, and $W_{\rm g}$ is the gate-width of the device. In the same way, the intrinsic gate-to-source capacitance $C_{\rm gs}$ is equal to 57.89 fF, which remains close to the expected physical value based on the first-order expression $C_{\rm gs}=\varepsilon_{\rm InAlAs}L_{\rm g}W_{\rm g}$/$t_{\rm InAlAs}$ (giving $C_{\rm gs}$ $=$ 42 fF), where $\varepsilon_{\rm InAlAs}$ and $t_{\rm InAlAs}$ are the barrier permittivity and thickness, respectively, whereas $L_{\rm g}W_{\rm g}$ corresponds to the gate contact area^[15].

The $S$-parameters comparison of the small signal model with those measured is shown in Figure 9, where it can be seen that the $S$-parameters of the model and those measured were consistent with each other from 0.5-110 GHz. To the best of the authors' knowledge, this is the first reported full band small-signal model from 0.5 to 110 GHz based on measurements in domestic circumstances. Thus, it is proven that the small-signal model is much more accurate from 0.5-110 GHz than the extrapolated model.

5. Conclusion

90-nm InP-based PHEMTs have been designed and fabricated. Due to the scaling gate size and the high indium composition in the channel, good performances have been achieved. The maximum saturation current is 755 mA/mm, the peak extrinsic transconductance is 1006 mS/mm, $f_{\rm t}$ and $f_{\rm max}$ of this transistor are 180 and 264 GHz, respectively. The $S$-parameters of the small signal model from 0.5-110 GHz are consistent with those measured from 0.5-110 GHz, so it is proven that the small signal model is much more accurate from 0.5-110 GHz. Further, the small-signal model from 0.5 to 110~GHz provided convenience for MMICs design.

Acknowledgement The authors would like to thank Dr. Huang Hui from the National Institute of Metrology, China for their helpful discussions and strong technical support on 0.5-110 GHz measurements. The authors also would like to express their appreciation to all the members of the Hebei Semiconductor Research Institute for their help.