1. Introduction

As the technology shrinks, there is a need for novel devices due to the short channel effects experienced by conventional bulk MOSFETs^{[1, 2]}. FinFETs have emerged as a promising candidate to replace conventional MOSFETs, with better gate control, low leakage current, etc. There are two types of FinFETs, also known as double gate (DG) devices, namely the simultaneously driven DG (SDDG) and the independently driven DG (IDDG). The SDDG has both gates tied together and is like a three terminal device, whereas the IDDG has two separate gates and behaves like a four terminal device^{[3, 4]}. The two gates of the IDDG FinFET can be biased independently whereas the SDDG FinFET can receive only one gate bias.

In the receiver chain of RF communication systems, the low noise amplifier (LNA) is the first active block after the antenna. The main function of the LNA is to amplify the weak signal without adding self-generated noise. The overall performance of the system is determined by the LNA. Since the LNA is in the high frequency section the input impedance is an important metric in deciding the LNA performance. A narrow band LNA provides input impedance matching around the operating frequency. As the technology shrinks, the impact of process variation becomes more significant^{[5, 6]}. Process variations affect the device parameters there by LNA performance.

In this work, a 45 nm gate length IDDG FinFET based cascoded narrow band LNA (Figure 1) operating at 5 GHz is designed and studied to assess its process variation. Five parameters (four geometrical parameters and one non-geometrical parameter), gate length, channel width, gate oxide thickness, fin width, and channel doping concentration, of T1, T2 and T3 (Figure 1) are considered for process variation. As already stated, the two gates of the IDDG device can be biased separately. When one of the gates of the IDDG device receives the signal, the other gate can be provided with a separate bias and is used to mitigate the impact of process variation. The rest of this paper is organised as follows. The simulation methodology is discussed in Section 2. The simulation results are discussed in Section 3. Finally, Section 4 provides the conclusion.

2. Simulation methodology

All the simulations in this study are performed using a 45~nm FinFET PTM model^[7] in a tanner (T-SPICE) circuit simulator. Figure 1 shows the IDDG FinFET-based LNA circuit used in this study. It can be observed from Figure 1 that T1 and T2 are operating in IDDG mode. One of the gates is receiving the signal while the other gate is grounded, see Figure~1. Generally, the real part of the input impedance matching is achieved by using a common source LNA with a source degeneration inductor. The circuit in Figure 1 does not use any degeneration inductor, instead it uses the non-quasi-static (NQS) effects visible at high frequencies^[8]. The disadvantage of this topology is that it couples the transistor dimensions with the input impedance matching, i.e. to some extent the LNA gain is constrained. The imaginary part, i.e. the capacitance of the input impedance, is nullified at the given frequency by connecting an appropriate inductor $L_{\rm g}$ at the gate.

The size of the cascode transistor T2 is same as T1. T3 is a current mirror and it sets the biasing for T1. A capacitor $C_{\rm e}$ is added in parallel with $C_{\rm gs}$ of T1. This is added to reduce the effective quality factor $(Q)$ of the input network and thereby it improves the linearity (IIP3) of the amplifier^[9]. The on-chip inductors $L_{\rm g}$ and $L_{\rm d}$ have a $Q$ of 5 and the resistance added in series to the inductor is given by the following expression. Similarly, for all capacitances used, resistances have been added to model the effect of finite $Q$.

$R=\frac{2\prod f \times {\rm inductor\_value}}{\rm quality\_factor}.$

(1)

The circuit is operated at the supply voltage of $V_{\rm dd }$ $=$ 1~V. The operating frequency $(f)$ of the LNA is 5 GHz, i.e. the input impedance 50 $\Omega$ purely real occurs at 5 GHz.

The LNA parameters, the real and imaginary parts of input impedance, the gain and noise figure (NF), are extracted through regular AC simulations. The components used in the LNA are listed in Table 1 and the performance parameters of the designed LNA are shown in Table 2. Figures 2, 3, 4 and 5 depict the real and imaginary parts of the input impedance, gain and NF plots, respectively, as a function of frequency. These values can be compared with the 90 nm and 45 nm technology experimental results^{[10, 11]}.

The gate length ($L$), channel width ($W$), gate oxide thickness ($T_{\rm ox})$, fin width ($T_{\rm si})$, and channel doping concentration ($N_{\rm ch})$ of three transistors (T1, T2 and T3 in Figure 1) are varied by $\pm$ 10 % from their nominal value to capture the impact on the input impedance of the LNA. As there are variations in the three transistors (T1, T2 and T3) there are 15 parameters to vary. Table 3 gives the range for the various parameters studied in this paper. Plackett-Burman design of experiment (DOE) is performed over these 15 variables.

3. Results and discussion

As mentioned earlier, the Plackett-Burman experiment (PBE) is conducted for 15 important and sensitive parameters of the transistors T1, T2 and T3, namely gate length ($L_{1}$, $L_{2}$ and $L_{3})$, channel width ($W_{1}$, $W_{2}$ and $W_{3})$, gate oxide thickness ($T_{\rm ox1}$, $T_{\rm ox2}$ and $T_{\rm ox3})$, fin width ($T_{\rm si1}$, $T_{\rm si2}$ and $T_{\rm si3})$ and channel doping concentration ($N_{\rm ch1}$, $N_{\rm ch2}$ and $N_{\rm ch3})$. Table 4 shows 16 runs of the PBE for the 15 variables. Table 5 shows the impact of process variations on the LNA parameters such as input impedance (both real part and imaginary part), gain and NF.

It can be observed from Table 5 that the variations in the process parameters of the device affect both the real and imaginary parts of the input impedance of the LNA, i.e. they are no longer matched to 50 $\Omega$ purely real. It can be observed from Table 5 that the variation in the real and imaginary parts of the input impedance falls into one of the cases shown in Table 6.

For all the cases listed in Table 6, the input impedance matching, 50 $\Omega$ purely real, is achieved by adjusting the gate2 biases of T1 and T2 (Figure 6). Figure 6 is essentially the same as Figure 1 except that the second gate is biased from two external voltage sources. To facilitate understanding of the mitigation of process variation through this technique, we have studied a simple IDDG device in a common source configuration. Figure 7 shows this circuit arrangement. Figure 8 shows the variation of input impedance as a function of gate 2 bias voltage when fixing gate1 at 0.5 V. From Figure 8 we can see that both the real and imaginary parts of the input impedance can be varied by changing the gate 2 bias. This behavior can be used to match the input impedance of the LNA to 50 $\Omega$ purely real. The mitigation can be performed by changing the gate 2 biases of both T1 and T2 (Figure 6). The change in gate 2 bias ($V_{\rm G2})$ of transistors T1 and T2 causes variation in $g_{\rm m}$, $C_{\rm gg}$ and $C_{\rm gd}$ which are the cause of the input impedance variation. Since $g_{\rm m}$ affects $r_{\rm i}$ (resistance due to the NQS effect) the real part of the input impedance varies. Variation in $C_{\rm gg}$ and $C_{\rm gd}$ directly impacts the imaginary part of the input impedance^[12].

Table 7 gives the value of the input impedance before matching and after matching along with the required T1 and T2-gate 2 bias voltages. The compensation of mismatched input impedance is performed using the method depicted in Figure 9. It can be seen from Table 7 that the matching process does not degrade the gain and NF significantly.

The impact of the resistances $R_{\rm B}$ and $R_{\rm e}$ on the input impedance are studied separately and Figures 10 and 11 show the corresponding plots. Using the same technique the variation is mitigated. Table 8 lists the impact of $R_{\rm B}$ and $R_{\rm e}$ on the input impedance, for two different $R_{\rm B}$ and $R_{\rm e}$ values, before and after matching.

4. Conclusion

Techniques to compensate the impact of process variation on a narrow band cascoded LNA topology have been investigated in this work. A 45 nm gate length IDDG FinFET-based LNA was designed to produce a proper input impedance, gain and NF. The designed LNA was allowed to go through variations in five different parameters, gate length, channel width, gate oxide thickness, fin width and channel doping concentration. The impact of variations on the LNA input impedance (both real and imaginary) was mitigated by setting up an appropriate bias at the second gate (gate2 of T1 and T2 in Figure~6). The compensation achieved through changing the common source and common gate devices was successful for all the cases following the method proposed and compensation was achieved without compromising the gain and NF of the LNA.