1. Introduction

As the CMOS process approaches tens of nanometers, such as 65 nm, 40 nm, and more advanced processes are being developed, the use of asynchronous successive approximation register (SAR) analog-to-digital convertors (ADC) are blooming due to their high energy efficiency. In contrast from synchronous SAR ADCs, asynchronous SAR ADCs have the same clock rate as the sampling rate. The internal beginning signal of each comparison step is generated by an ending signal of the last time comparison. Current state-of-the-art SAR ADCs are likely to have hundreds of mega-Hz sampling and medium resolution with FoMs of less than 100 fJ/conversion-step^[1]. ADCs with these specification are likely to be implemented by flash and folding ADCs, which are much more power hungry than SAR ADCs.

However, there are several factors that prevent SAR ADCs from further accelerating to few Giga-Hz rate performance^[2]. The first and foremost factor is the settling time issue. Inside a SAR ADC, the most time-demanding process is the most significant bit capacitor's (MSB) settling time. In other words, it is the time from the end the first comparison to the beginning of the second comparison. A conventional SAR ADC requires that the settling error of all comparisons should be less than 1/2~LSB, meaning that there is a long settling time for the MSB capacitor. Otherwise, there would be a missing code for certain analog inputs. Take the first order RC settling process as an example. The MSB settling time is known as,

$t_{\rm MSB}> (N+1)R_{\rm on}C_{\rm MSB}\ln 2,$

(1)

where $N$ is the ADC's resolution bit, $R_{\rm on}$ and $C_{\rm MSB}$ represents the time constant. For the rest bits, the settling time reduces exponentially due to the capacitor scaling. Therefore, $t_{\rm MSB}$ is the most critical time determining the SAR ADC's speed. %From the point of view of implementation, the settling time is estimated by cascading several stages of the inverter-based delay line. Although some redundancy based architectures have been proposed^[3], the simplest method to accelerate SAR ADCs is to minimize $C_{\rm MSB}$ or the unit capacitor size.

Another issue related to the settling are the ripple effects of the reference voltage, especially for hundreds of Mega-Hz SAR ADCs, where traditional active reference buffers are likely to fail to drive the big capacitive load. The current solution is to utilize very large on-chip decoupling capacitors to filter the reference voltage ripples. The decoupling capacitors are positively proportional to the total capacitor size and unit capacitor size. %Unfortunately, this is area consuming. %Some other issues include the number of comparison step for a SAR ADC. Some methods like 2-b/step can relax the number and accelerate the ADC's rate^[1].

Apparently, there is a straight forward way to accelerate the ADC's speed and avoid large area decoupling - minimizing the capacitor sizes so that they are as small as possible. A small size capacitor reduces the load of the settling process, as well as the driving requirement of the reference voltage. Moreover, smaller size capacitors can save more power dissipation. Note that the settling power consumption remains as,

$P_{\rm settling}=\frac{1}{2}\alpha V^2_{\rm Ref}C_{\rm load},$

(2)

where $\alpha$ is denoted as the switch frequency for the reference driver. However, foundries do not provide customized small capacitors that are suitable to SAR ADCs.

Traditionally, only metal-insulator-metal (MIM) capacitors are provided, which are area consuming and not suitable for application in SAR ADCs. MIM capacitors feature a high capacitance density and a strict DRC rule, resulting in a both power hungry and big-area capacitive tank. In contrast from MIM capacitors, MOM capacitors use the oxide between metals as a dielectric to build a capacitor. Customized 3-D MOM capacitors are now appearing that are suited to high speed SAR ADC design. In this paper, an umbrella-shaped 3-D MOM capacitor with around 1-fF capacitance is proposed. To verify its effectiveness, a capacitive DAC with the proposed capacitors is fabricated. %Simulation and measurement results meet the design expectation. %Section 2 will review other customized 3-D MOM capacitors, and Section 3 will introduce the proposed one. %The circuit implementation of the capacitive DAC would be detailed in Section 4. %Fabrication and experimental result would be demonstrated in Section 5, and section 6 concludes the paper.

2. Review of a MOM capacitor for SAR ADCs

2.1 Capacitor requirement for SAR ADCs

To satisfy the operation of SAR ADCs, not only the capacitance but also the parasitics need to be counted. A general model of a MOM capacitor is given in Figure 1(a). In Figure 1(a), $C_{\rm pB}$ and $C_{\rm pT}$ stands for the parasitic on the bottom and top plate of the MOM capacitor. $C_{\rm u}$ is the unit capacitor that is expected. $\Delta C$ represents the extra coupling factor between bottom and top plate. This could be caused by the variation among capacitor tanks, but is more likely to be caused by the extra coupling between routing wire and one certain plate of the capacitor. This factor is of the most concern for MOM capacitors compared with MIM capacitors, especially from the view of layout.

From the aspect of precision, both $\Delta C$ and $C_{\rm pB}$ would affect the linearity of the ADC. Assuming the cases without attenuating capacitor and that only MSB capacitor has these parasitics, the linearity issue is as follows,

$V_{\rm in}=\frac{V_{\rm Ref}C_{\rm u}}{C_M+C_{{\rm Total}(M-1)}+C_{\rm pT}}\left[D_{\rm o}+S_{\rm M}\frac{\Delta C}{C_{\rm u}}\right],$

(3)

where $S_{\rm M}$ is bit decision of the MSB bit and $D_{\rm o}$ is the overall digital output. Apparently, the $S_{\rm M}\times\Delta C/{C_{\rm u}}$ term causes discontinuity and nonlinearity between $V_{\rm in}$ and $D_{\rm o}$. Equation (3) can be easily derived into capacitors of other bits. Although $C_{\rm pB}$ only affects in gain error in Equation (3), it would worsen the case when it comes to capacitive tanks with attenuating capacitors.

From the aspect of speed or settling time, the RC term in the bottom plate is the most critical issue. The lumped model in Figure 1(a) is too optimistic an approximation if the routing wire is too long. $C_{\rm u}$ also affects the settling. Note that both $C_{\rm u}$ and $C_{\rm pB}$ term accumulate for MSBs by an order of $2^N$.

2.2 Previous custom 3-D MOM capacitor

Several 3-D MOM capacitors have been proposed for high performance SAR ADCs, as shown in Figures 1(b), 1(c) and 1(d). The dark shadowed metal is the bottom plate, whereas the light shadowed metal is the top plate.

Figure 1(b) is an almost 2-D MOM capacitor with top plate contoured to the bottom plate^[2]. The sidewall-like shape tends to share one side of wall with the next capacitor. The capacitor has a unit capacitance of 1.3 fF and parasitic of 0.7 fF. Note that this structure has a high value $\Delta C/C_{\rm u}$, which needs very careful layout work to maintain precision.

Figure 1(c) is a symmetric 3-D MOM capacitor^[4]. In reality, the pattern was stacked and repeated in a multi-layer method. It also features a good matching nature over the peripheral effect. Its unit capacitance is 2.6 fF. The finger-based MOM capacitor provided by foundry's PDK is much like this topology, except that more layers are exploited. %However, the symmetric structure, in other words, $C_{pB}=C_{pT}$, makes no room for more optimization.

Figure 1(d) shows a 3-D MOM capacitor which has a pillared top plate enclosed by its bottom plate^[5]. Considering it advanced technology, the unit capacitance is 0.78 fF with an area of 1 $\mu$m$^2$. The motivation of the pillar-based is to have a very clear top-plate node; unfortunately, there is a penalty of a huge parasitic of the bottom plate. These parasitics may deteriorate the settling process.

Some other structures have also been proposed, like the sandwich-like structure in Reference {^[3]}. But they cannot overweigh those mentioned in terms of performance.

3. Proposed custom 3-D MOM capacitor

3.1 MOM topology

In contrast from these previous custom capacitors, the proposed capacitor takes settling as a priority. In other words, it minimizes $C_{\rm pB}$ as much as possible. Figure 2 shows the detail of the proposed 3-D MOM capacitor, including its cross section, top view, and bottom view. Generally speaking, the proposed MOM capacitor is a complementary version of that in Figure 1(d). It has a pillar based bottom plate, with edge expanding at the level of metal 6. The top plate is enclosed by the bottom plate in all directions. In this way, the distance between the bottom plate and top plate is minimized, as the DRC and DFM rule allows. Thus, the capacitive density is kept high, resulting in an area of $2 \times 2$ $\mu$m$^2$ for 1 fF capacitance.

The capacitor starts from the third layer of metal (M3), because M1 and M2 have high amounts of parasitic with the silicon ploy and substrate. The edge expanding topology on M3 and M6 is to increase the coupling area between the two plates. Considering routing, M3 is chosen as an octagon to avoid asymmetry of the optical lithography. The routing layer of bottom plates is M3, and that of the top plate is M7. It is appreciated that routing M3 and M7 are perpendicular. To offer a more direct impression, a 3-D shape of the proposed MOM capacitor is illustrated in Figure 3. The back side is separated from the center part in the figure so as to reveal the inner structure. Also, the front side is neglected for the same reason.

RC extraction EDA tools show all the capacitance, as demonstrated in Table~1, according to the general model in Figure 1(a). It is obvious that the proposed structure suffers a top plate parasitic issue. As the outer side of the MOM capacitor, the top plate may couple with nearby metals. For example, there is a closed dummy cell side wall, thus increasing $C_{\rm pT}$. However, $C_{\rm pT}$ only causes a gain error and does not affect linearity, according to Equation (3).

According to Equation (3), the SAR ADC's resolution is limited by the $\Delta C/C_{\rm u}$ factor. EDA tool extraction shows that $\Delta C/C_{\rm u}$ is less than $0.3%$, or about 8-bit resolution. However, due to the big value of $C_{\rm pT}$, only a 2 bit capacitor is allowed to be implemented after an attenuating capacitor.

3.2 Comparison among custom 3-D MOM capacitors

The proposed MOM capacitor features a very low extra coupling between the two plate and a minimal driving load for the bottom plate, though not fit for capacitive tanks with attenuating capacitors.

The low coupling characteristic overweighs the MOM capacitors in Figures 1(b) and 1(c). The main capacitance of the proposed capacitor is contributed by the enclosure structure. Routing wires far away from the pillar can be ignored for less than 8b resolution. Even for higher precision, it is easy to match the extra coupling with a careful layout job. On the other hand, the MOM capacitors in Figure 1(b) and 1(c) have complex routing coupling models. The minimal driving load characteristic overweighs the MOM capacitors in Figure 1(d). This is a key contribution for fast settling. Unlike the huge surface area of the bottom plate exposed to the overall environment in Figure 1(d), the proposed capacitor has a small volume bottom plate. As a result, the coupling of the bottom plate is also low. %Nevertheless, the surface area of the MOM capacitor in Fgure 1(d) is of immense size.

Table 1 also includes a quantitative comparison among capacitors based on the general electrical model given in Figure~1(a). These figures are slightly different from its original figures from their reference. To be fair, all of the capacitors are drawn under the same area ($2\times2$ $\mu$m$^2$) with the same process (TSMC CMOS 65 nm LP 1P9M process).

One apparent drawback of the proposed capacitor is the high proportion of the top plate parasitic. The parasitic term is highly unfriendly for a capacitive tank with attenuating capacitors. Any top plate parasitic on the other node of the attenuating capacitor would cause a nonlinearity term,

$V_{\rm in}\approx\frac{V_{\rm Ref}C_{\rm u}}{C_{\rm Total}}\left[\sum^{\rm MSB}_{\rm Atten.Bit}2^iD_i+\sum^{\rm Atten.Bit}_{\rm LSB}\left(1-\frac{C_{\rm pON}}{C_{\rm Total}}\right)2^iD_i\right],$

(4)

where $C_{\rm pON}$ is the bad parasitic and the accumulative effect of the $C_{\rm pT}$ in our capacitor model. A detailed analysis and expression can be seen in Reference {^[6]}.

4. Test chip circuit implementation

To verify the effectiveness of the capacitor, a capacitive DAC is implemented by 1P9M 65 nm LP CMOS technology. The circuit topology is shown in Figure 4.

The test chip has a single-ended capacitive DAC architecture. To investigate the RC extraction EDA tools' effectiveness, the last bit is implemented by an attenuating capacitor. A source-follower based buffer is utilized to make the output track the charge conservation node. The RST and CLK signals are generated as a two-phase non-overlapping pattern. Periodical RST signal refreshes conservation node every cycle.

A $C_{\rm fix}$ capacitor is inserted at the conservation node. This additional capacitor is used to estimate the capacitance of the MOM device. The relationship between the LSB voltage step and $C_{\rm fix}$ follows,

$V_{\rm LSB}=V_{\rm ref} \frac{C_{\rm u}}{2^NC_{\rm u}+C_{\rm pTtotal}+C_{\rm fix}} A_{\rm SF},$

(5)

where $C_{\rm pTtotal}$ is the estimated value of the accumulative effect of the top plate parasitic, including the coupling among side-wall dummy cells. $A_{\rm SF}$ is the gain of source follower buffer.

NMOS transistors are put under the capacitive tank, which is the most area-efficient way to decouple the reference voltage^[2]. NMOS transistors are configured as MOS capacitors with high capacitance density but low linearity. Considering that the voltage source charges and discharges in a short instance, an inductive bonding wire may cause an additional reference problem for slow settling. Although on-chip regulation circuits work out for this problem, their power consumption may be several multiples of the ADC core. Another solution is to employ large decoupling capacitors as a charge reservoir to reduce the reference ripple. The NMOS capacitors play such roles in the design and give a large ratio between the high volume decoupling and the loading capacitor partially, about 1000 over 1.

5. Experiment result

The proposed MOM capacitor and the test bench capacitive DAC were fabricated by TSMC 65 nm CMOS Low power technology, under a power supply of 1.2 V. Figure 5 shows the layout die photo of the DAC. The capacitive tank covers the major area. The overall active devices cover an area of 36 $\times$ 32~$\mu$m$^2$. At a conversion rate of 100 MHz, the power consumption of the DAC is 160 $\mu$W, excluding the source-follower based buffer. The buffer dissipates 480 $\mu$W to drive the on board load and test equipment.

Static measurements are implemented to reveal the post silicon linearity. The result is shown in Figure 6, where both INL and DNL are less than $\pm$0.5 LSB for the 6-bit resolution. The average LSB step is 4.77 mV. When we substitute the voltage step into Equation (5), the $C_{\rm u}$ is very close to 1 fF, showing a good estimation by RC extraction EDA tools.

However, the periodical ripples occurring in the DNL waveform show the unpromising character of the actuating capacitor. Quantitative analysis suggests that the attenuating capacitor is over $50%$ greater than expected, which is not demonstrated by the EDA tools. This phenomenon meets the prediction given in Section 3.2, in that the proposed MOM capacitor does not have good performance when it comes to attenuating structure.

6. Conclusion

This paper proposes a 3-D MOM capacitor and its test bench circuit, a capacitive DAC. The proposed 3D MOM capacitor has a unit capacitance of 1-fF. The capacitor has a pillar based bottom plate, which is enclosed by a top plate like an umbrella. Compared with other custom capacitors, the capacitor features low extra decoupling and fast settling A 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology under a power supply of 1.2 V. Due to the low capacitance, the DAC only consumes a power dissipation of 160~$\mu$W at a rate of 100 MS/s. Static measurements are performed, demonstrating that both INL and DNL are less than $\pm0.5$ LSB, even with one bit attenuating structure.