1. Introduction

The increasing energy and bandwidth demand on the current telecommunication systems drives the needed transmission bandwidth of communication systems to a higher level. The bandwidth limit on conventional copper interconnects makes it challenging to implement transceiver circuits at tens of gigabits per second operation. Fortunately, optoelectronic integrated circuits (OEIC) can overcome the problems of power consumption, speed limitation, and cross noise in conventional interconnects, which integrate silicon PD with preamplifier on the same substrate, minimizing the input parasitic capacitance and inductance of the circuit^{[1, 2]}. The transimpedance amplifier (TIA) is required to convert the current pulse produced by the PD into a voltage pulse with an amplitude and shape suitable for the subsequent processing^{[3, 4]}. Thus, the TIA is a critical element as their speed and sensitivity set the maximum data rate as well as the tolerable channel loss. The regulated cascode (RGC) topology is currently a very popular configuration during the input stage of TIA at least partly due to its high gain wide bandwidth and comparatively low power consumption^[5]. Nevertheless, the bandwidth of RGC TIA can be further improved by modifying the topology structure.

The signal in a weak photocurrent that has been amplified by a TIA with a low signal-to-noise radio (SNR) cannot be recovered in post-equalization. By contrast, a pre-equalization method may be a better solution. This method compensates for the transferred signal by inserting a frequency-compensation circuit, such as a series inductive peaking network^{[6, 7]} or capacitance degeneration technology^{[8, 9]} into the front of the optical receiver^[10]. In general, the effective signal can be compensated before being overwhelmed in noise due to the equalization generated in the input port of the TIA.

In this paper, the traditional RGC TIA architecture is modified with pre-equalization topology to meet the 10 Gb/s short-distance optical interconnects without degrading the circuit sensitivity or using any off-chip components. One on-chip MIM capacitor is placed externally to match the actual PD capacitance. Capacitance degeneration and series inductive peaking networks are used for pole-zero cancellation and bandwidth enhancement.

2. Pre-equalization RGC TIA

2.1 Modified RGC input stage

Among all the building blocks in the OEIC, the TIA is the most critical one in this design. It is a well known fact that RGC input configuration can achieve better isolation within the large PD capacitance via local feedback mechanisms. Figure 1(a) shows the schematic diagram of the conventional RGC with a PD, which converts the incoming optical power to a signal photocurrent $I_{\rm PD}$. The common-source (CS) amplifier consists of M2 and $R_{3}$ operate as a local feedback mechanism and regulate the common-gate (CG). According to the small-signal analysis, the input resistance of the RGC circuit is given by

$Z_{\rm in1} =\frac{1}{g_{\rm m1} (1+g_{\rm m2} R_3 )}.$

(1)

It is clearly seen that the input resistance decreased because the transconductance ($G_{\rm m})$ is $1+g_{\rm m2}R_{3}$ times larger than that of the conventional common gate (CG) amplifier input stage, where $1+g_{\rm m2}R_{3}$ is the voltage gain of the local feedback CS stage that consists of M2 and $R_{3}$. Thus, RGC stage acts as a buffer between the PD and the TIA stage and reduces the dependence of the TIA on the value of the PD capacitance.

In addition, the voltage gain can be enormously improved by using a cascode technique. As shown in Figure 1(b), the cascode transistor M3 is placed between the output of the CS amplifier and the gate of M1. Thus, the transistor M2, M3 and load resistor $R_{3}$ constitute the cascode amplifier for the local feedback mechanism in the modified RGC circuit. The input resistance of the modified RGC circuit is given by

$Z_{\rm in2} =\frac{1}{g_{\rm m1} [1+g_{\rm m2} (g_{\rm m3} +g_{\rm mb3} )r_{\rm o2} r_{\rm o3} \vert \vert R_3 )]},$

(2)

where $g_{\rm mb3}$ is the body transconductance of M3, $r_{\rm o2}$ and $r_{\rm o3}$ are the small signal output resistances of the transistors M2 and M3 respectively. Equation (2) shows that the cascode local feedback mechanism boosting the $G_{\rm m}$ compared to the conventional RGC circuit. Furthermore, this mechanism can reduce the Miller effect of M2 due to the gate-drain capacitance $C_{\rm gd}$ between the input node and the drain of M2.

Pre-equalization methods entail compensating for the transferred signal by inserting the frequency-compensation circuit into the front of the optical receiver. As a pre-equalization method, the RGC circuit with a cascode feedback mechanism alleviates the bandwidth limitation due to the input pole consist of $C_{\rm gs2}$ and $Z_{\rm in}$. However, the large parasitic capacitance of PD still deteriorates both the bandwidth and the noise performance of the system.

2.2 Series inductive peaking

In this paper, series inductive peaking technology has been used to overcome the aforementioned problem. As shown in Figure 1(b), the inductor $L_{1}$ is inserted between $C_{\rm PD}$ and $C_{\rm gs2}$, which causes the inductive-series to peak at the $\pi$-network. Following a similar approach in Reference ^[11], the current mode transfer function of this $\pi$-peaking network can be expressed as the following third-order expression:

$$\begin{split} \frac{I_{\rm IN} }{I_{\rm PD} } {}& =\frac{1}{s^3R_1 LC_{\rm PD} C_{\rm gs2} +s^2LC_{\rm gs2} +sR_1\left( {C_{\rm PD} +C_{\rm gs2}} \right)+1} \\[3mm]& =\frac{1}{\left( {\dfrac{s}{\omega _0 }} \right)^3\dfrac{k}{m}\left( {1-k} \right)+\left( {\dfrac{s}{\omega _0 }} \right)^2\dfrac{1-k}{m}+\dfrac{s}{\omega _0 }+1}, \\ \end{split}$$

(3)

where $k = C_{\rm gs2}/(C_{\rm PD}+C_{\rm gs2})$ and $m=R_{1}^{2 }(C_{\rm PD}+C_{\rm gs2})/L$. Significant bandwidth extension ratio (BWER) can be achieved by choosing different values for variables $k$ and $m$, as shown in Figure 2, where the frequency is normalized to the 3-dB frequency ($\omega _{0 }=1/(C_{\rm PD}+C_{\rm gs2})R_{1})$ of the uncompensated case with $L$ $=$ 0. However, it is important to avoid values that cause large gain ripple in the frequency response, as this would introduces large group delay variation and results in significant signal distortion.

Figure 1(c) shows the small-signal model of the pre-equalization modified RGC circuit, where $C_{\rm d2}$ and $C_{\rm s3}$ are the total parasitic capacitances in the source of the M3 and the drain of the M2. The inductor $L_{2}$ inserted into the cascode feedback amplifier with $C_{\rm d2}$ and $C_{\rm s3}$ to cause the largest improvement in bandwidth. This is because the sizes of the cascode transistors are large enough for achieving the $G_{\rm m}$-boosting. With these applications, the dominant pole of the modified the RGC stage moves to the output of the RGC stage and the input pole becomes the secondary dominant one, thus achieving a wider bandwidth.

Figure 3 shows the schematic diagram of the proposed pre-equalization RGC TIA circuit. Since the RGC stage operates as a current buffer, a second voltage gain stage is required. The series inductor $L_{3}$ is inserted into the drain capacitance of the RGC stage and the gate capacitance of the gain stage in a series inductive-$\pi$-network. Consequently, the RGC dominant pole is compensated by this network and the new dominant pole is pushed to the input stage. However, due to the pre-equalization mechanism, the bandwidth of the entire RGC TIA will reach a higher level.

2.3 Novel miller capacitance degeneration

In addition to use RGC input stage, it is also possible to compensate the dominant pole of the overall circuit with a zero, which could be accomplished by capacitive degeneration structure. Figure 4 shows the schematic of a capacitive degeneration common source stage.

The equivalent transconductance of the gain cell is given by

$G_{\rm m} =\frac{g_{\rm m} \left( {1+sR_{\rm s} C_{\rm s} } \right)}{1+g_{\rm m} R_{\rm s} +sR_{\rm s} C_{\rm s} },$

(4)

which contributes a zero at ($R_{\rm s}C_{\rm s})^{-1}$ and a pole at ($1 + g_{\rm m} R_{\rm s})/R_{\rm s}C_{\rm s}$. Obviously, the zero result from the capacitance degeneration structure could be used to compensate the dominant pole of the circuit. The bandwidth is therefore determined by the second lowest pole of the circuit.

The proposed gain stage consists of two CS amplifiers with novel miller capacitance degeneration method. As can be intuitively shown in Figure 3, the shunt capacitor $C_{1}$ can be converted to a couple of equivalent miller capacitors. Assuming that A is the voltage gain between the two nodes of $C_{1}$, which equal to the product of the CS amplifier (M4, $R_{5})$ and the source follower's gain (M5, $R_{6})$. The equivalent split capacitors $-(A$-1)$C_{1}$ and [($A$-1)/$A$]$C_{1}$ can produce zeros with $R_{4}$ and $R_{6}$ to respectively cancel the poles at the gate of M4 and M5. Thus, the bandwidth is therefore further extended. The output buffer stage consists of M6 and M7 for driving the 50 $\Omega$ loads required for measurement. In addition, to alleviate the output node bandwidth degradation, the active inductance peaking technique is implemented.

3. Simulation and measurement results

The proposed TIA circuit simulation is carried out using Cadence Spectre RF with UMC 0.18 $\mu$m standard CMOS technology with a single poly and six aluminum layers. The $S$-parameter response simulation result is shown in Figure 5 with and without the pre-equalization measurement. The simulation gain is about 18.3 dB with a -3 dB bandwidth of about 9.6 GHz. The peak in the 3 GHz is produced by the miller capacitance degeneration. Figure 6 shows the post-layout simulated eye-diagram corresponding to 10 Gb/s, 100 $\mu$A input current with 2$^{31}$-1 pseudorandom binary sequence (PRBS). The maximum output swing of the TIA is about 190 mV$_{\rm pp}$.

Figure 7 shows the chip micrograph of the proposed TIA and the dimension is 700 $\times$ 850 $\mu$m$^{2}$. $L_{1}$-$L_{3}$ are implemented using a planar spiral inductance to ensure a monolithic implementation. The quality factor is not the primary issue in this case because it is used for the bandwidth enhancement. An on-chip MIM capacitor $C_{\rm pd}$ of 0.3 pF is used to mimic the effect of the PD parasitic capacitance, combined with the parasitic capacitance of the input pad, the total input parasitic capacitance is about 0.35 pF. In order to reduce the parasitic influence on the behavior of the amplifier, the interconnection lines are designed as short as possible.

Two-port on wafer $S$-parameters were measured using Cascade Microtech Coplanar ground-signal-ground (GSG) probes and the network analyzer (N5242A) of Agilent Technologies. The resulting $S$-parameter of the CMOS TIA is shown in Figure 8. $S_{21}$ is approximately 8.4 GHz, and quite flat up to 7 GHz. The resonance peak in 8 GHz is higher than the simulation values, what is possibly caused by the less-than-ideal inductances and inaccurate parasitic inductance in the metal line between the power supply and pad. $S_{11}$ is less than -10 dB up to 10 GHz, and $S_{22}$ is less than -10 dB up to 15~GHz.

The measured transimpedance response and the group delay response are shown in Figure 9. The transimpedance gain $Z_{\rm t}$ is calculated from measured $S$ parameters based on the equation:

$Z_{\rm t} =Z_{21} =\frac{2S_{21} }{(1-S_{11} )(1-S_{22} )-S_{21} S_{12} }\times Z_0 ,$

(5)

with $Z_{0}$ equal to 50 $\Omega$. The transimpedance response exhibits a 8.2 GHz bandwidth and 57 dB$\Omega$ transimpedance gain with very small ripple effects. The group delay is calculated from the measured phase response, we can then observe that the group delay is about 70 $\pm$ 30 ps. As shown in Figure 10 the measured input referred noise current spectral density is 21 pA/$\sqrt{\rm Hz}$ up to 8 GHz, which is higher than the simulated one. This difference is possibly due to an inaccurate noise model, additional parasitic elements and substrate noise/losses that were not considered in the simulation. The chip consumes only 22 mW DC power from a single 1.8 V supply. Table 1 lists the performance summary with the other works in the similar technology.

4. Conclusion

10 Gb/s pre-equalized RGC TIA was designed and fabricated using UMC 0.18 $\mu$m CMOS technology. The photocurrent generated from the PD can be compensated by a broadband series inductive $\pi$-network and the $G_{\rm m}$-boosting technique in the pre-equalized RGC TIA. A novel miller capacitance degeneration method was designed for further improving the bandwidth during the gain stage. The measurement results show that this TIA meets the specification for 10 Gb/s optical interconnects.