Abstract: To build an accurate electric model for through-silicon vias (TSVs) in 3D integrated circuits (ICs), a resistance and capacitance (RC) circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys's Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from 10 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.

Key words: 3D IC, through silicon via (TSV), parasitic extraction, floating random walk algorithm, metal-oxide-semiconductor (MOS) capacitance