Fig1.
The architecture of the ADC.
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| Citation: |
Jia Zhou, Lili Xu, Fule Li, Zhihua Wang. A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy[J]. Journal of Semiconductors, 2015, 36(8): 085008. doi: 10.1088/1674-4926/36/8/085008
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J Zhou, L L Xu, F L Li, Z H Wang. A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy[J]. J. Semicond., 2015, 36(8): 085008. doi: 10.1088/1674-4926/36/8/085008.
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A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy
DOI: 10.1088/1674-4926/36/8/085008
More Information
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Abstract
A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTA's layout design. Implemented in a 0.18-μ m CMOS technology, the ADC's prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply.-
Keywords:
- ADC,
- pipeline,
- body-effect,
- scaling down,
- parallel
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References
[1] [2] [3] [4] [5] [6] [7] [8] -
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