J. Semicond. > 2016, Volume 37 > Issue 1 > 015003
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SEMICONDUCTOR INTEGRATED CIRCUITS

A high-linearity and high-resolution delay line structure with a calibration algorithm in delay-based LINC transmitters

Yue Han, Shushan Qiao and Yong Hei

+ Author Affiliations

 Corresponding author: Han Yue,Email:hanyue@ime.ac.cn

DOI: 10.1088/1674-4926/37/1/015003

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Abstract: In order to overcome the bottleneck of low linearity and low resolution, an improved delay line structure is proposed with a calibration algorithm to conquer PVT (process, voltage and temperature) variations for an all-digital design. The chip is implemented in 0.13 μ m CMOS technology. Measurement results show that the proposed structure with the calibration algorithm can evidently improve the linearity and resolution of the delay line. The delay resolution is 2 ps and the root mean square jitter of the delay is 4.71 ps, leading to an error vector magnitude enhancement of 1.32 dB.

Key words: linear amplification with non-linear components (LINC), delay line, linearity, resolution



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Fig. 1.  LINC architecture.

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Fig. 2.  Two kinds of delay line structures.

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Fig. 3.  The proposed delay line structure.

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Fig. 4.  Cell delay changes with input transition and load capacitance.

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Fig. 5.  Simulated results of layouts for each structure.

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Fig. 6.  Simulated results of layouts with IC compiler.

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Fig. 7.  Proposed DCV line structure.

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Fig. 8.  Simulation of different resolutions in DCV line.

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Fig. 9.  Proposed calibration scheme for higher linearity.

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Fig. 10.  Test setup.

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Fig. 11.  Measurement of the delay line output with sweeping control codes.

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Fig. 12.  Measured delay nonlinearity for each stage.

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Fig. 13.  Measured Waveform of two delay line.

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Fig. 14.  he improved linearity of the delay line after calibration.

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Fig. 15.  The simulation circuit in ADS.

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Fig. 16.  Simulated constellation of the demodulated signal.

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Table 1.   Calibration procedure

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Table 2.   Comparison table.

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    Received: 15 January 2015 Revised: Online: Published: 01 January 2016

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      Article Navigation >  Journal of Semiconductors  > 2016  >  37(1): 015003
      Yue Han, Shushan Qiao, Yong Hei. A high-linearity and high-resolution delay line structure with a calibration algorithm in delay-based LINC transmitters[J]. Journal of Semiconductors, 2016, 37(1): 015003. doi: 10.1088/1674-4926/37/1/015003 ****Y Han, S S Qiao, Y Hei. A high-linearity and high-resolution delay line structure with a calibration algorithm in delay-based LINC transmitters[J]. J. Semicond., 2016, 37(1): 015003. doi: 10.1088/1674-4926/37/1/015003.
      Citation:
      Yue Han, Shushan Qiao, Yong Hei. A high-linearity and high-resolution delay line structure with a calibration algorithm in delay-based LINC transmitters[J]. Journal of Semiconductors, 2016, 37(1): 015003. doi: 10.1088/1674-4926/37/1/015003 ****
      Y Han, S S Qiao, Y Hei. A high-linearity and high-resolution delay line structure with a calibration algorithm in delay-based LINC transmitters[J]. J. Semicond., 2016, 37(1): 015003. doi: 10.1088/1674-4926/37/1/015003.
      shu

      A high-linearity and high-resolution delay line structure with a calibration algorithm in delay-based LINC transmitters

      DOI: 10.1088/1674-4926/37/1/015003

      • Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

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      • Corresponding author: Han Yue,Email:hanyue@ime.ac.cn
      • Received Date: 2015-01-15
      • Accepted Date: 2015-07-26
      • Published Date: 2016-01-25

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