A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 <i>μ</i>m CMOS

Dong Li; Qiao Meng; Fei Li

doi:10.1088/1674-4926/37/1/015004

J. Semicond. > 2016, Volume 37 > Issue 1 > 015004

SEMICONDUCTOR INTEGRATED CIRCUITS

A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS

Dong Li, Qiao Meng and Fei Li

+ Author Affiliations

Corresponding author: Meng Qiao,Email:mengqiao@seu.edu.cn

DOI: 10.1088/1674-4926/37/1/015004

Abstract: This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μ m 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 dB and spurious-free dynamic range (SFDR) of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm².

Key words: SAR ADC, switching scheme, SAR control logic, DAC, comparator

References

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Fig. 1. Block diagram of the proposed fully differential SAR ADC.

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Fig. 2. Flow chart of the proposed switching scheme.

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Fig. 3. Output waveform of the proposed switching method.

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Fig. 4. Equivalent circuit of the longest settling procedure of the proposed switching scheme.

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Fig. 5. The settling time against total capacitance of DAC.

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Fig. 6. Schematic of the bootstrapped switch.

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Fig. 7. Schematic of the dynamic comparator with pre-amplifier.

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Fig. 8. Schematic and timing diagram of the synchronous clock generator.

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Fig. 9. Diagram of the conventional SAR logic.

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Fig. 10. Diagram of the proposed SAR logic.

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Fig. 11. Timing diagram of the principle of the proposed SAR control logic.

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Fig. 12. Schematics of (a) the pulse generator and (b) the latch.

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Fig. 13. Chip microphotograph.

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Fig. 14. Measured FFT spectrum at 50 MS/s and 2.02 MHz input.

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Fig. 15. Dynamic performance versus input frequency.

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Fig. 16. Measured DNL and INL.

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Table 1. Performance summary.

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Table 2. Comparison with state-of-the-other-art works.

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Li Binqiao, Yu Junting, Xu Jiangtao, Yu Pingping. An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor[J]. Journal of Semiconductors, 2010, 31(7): 074010. doi: 10.1088/1674-4926/31/7/074010

Li B Q, Yu J T, Xu J T, Yu P P. An approach to obtain the pinch-off voltage of 4-T pixel in CMOS image sensor[J]. J. Semicond., 2010, 31(7): 074010. doi: 10.1088/1674-4926/31/7/074010.

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Received: 09 October 2015 Revised: Online: Published: 01 January 2016

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μ m 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 dB and spurious-free dynamic range (SFDR) of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm².

A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS

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