Fig. 1.
Architecture of CML interface system
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| Citation: |
Peipei Chen, Lei Li, Huihua Liu. A power-efficient switchable CML driver at 10 Gbps[J]. Journal of Semiconductors, 2016, 37(2): 025003. doi: 10.1088/1674-4926/37/2/025003
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P P Chen, L Li, H H Liu. A power-efficient switchable CML driver at 10 Gbps[J]. J. Semicond., 2016, 37(2): 025003. doi: 10.1088/1674-4926/37/2/025003.
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A power-efficient switchable CML driver at 10 Gbps
DOI: 10.1088/1674-4926/37/2/025003
More Information
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Abstract
High static power limits the application of conventional current-mode logic (CML). This paper presents a power-efficient switchable CML driver, which achieves a significant current saving by 75% compared with conventional ones. Implemented in the 130 nm CMOS technology process, the proposed CML driver just occupies an area about 0.003 mm2 and provides a robust differential signal of 1600 mV for 10 Gbps optical line terminal (OLT) with a total current of 10 mA. The peak-to-peak jitter is about 4 ps (0.04TUI) and the offset voltage is 347.2 mV @ 1600 mVPP.-
Keywords:
- power-efficient,
- switchable,
- CML,
- impedance matching
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References
[1] [2] [3] [4] [5] [6] [7] [8] [9] -
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