Abstract: A power balance static random-access memory (SRAM) for resistance to differential power analysis (DPA) is proposed. In the proposed design, the switch power consumption and short-circuit power consumption are balanced by discharging and pre-charging the key nodes of the output circuit and adding an additional short-circuit current path. Thus, the power consumption is constant in every read cycle. As a result, the DPA-resistant ability of the SRAM is improved. In 65 nm CMOS technology, the power balance SRAM is fully custom designed with a layout area of 5863.6 μm².The post-simulation results show that the normalized energy deviation (NED) and normalized standard deviation (NSD) are 0.099% and 0.04%, respectively. Compared to existing power balance circuits, the power balance ability of the proposed SRAM has improved 53%.

Key words: differential power analysis (DPA), static random access memory (SRAM), power balance, information security