J. Semicond. > 2016, Volume 37 > Issue 9 > 094001
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SEMICONDUCTOR DEVICES

A transformed analytical model for thermal noise of FinFET based on fringing field approximation

Savitesh Madhulika Sharma, S. Dasgupta and M. V. Kartikeyan

+ Author Affiliations

 Corresponding author: kartik@ieee.org

DOI: 10.1088/1674-4926/37/9/094001

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Abstract: This paper delineates the effect of nonplanar structure of FinFETs on noise performance. We demonstrate the thermal noise analytical model that has been inferred by taking into account the presence of an additional inverted region in the extended (underlap) S/D region due to finite gate electrode thickness. Noise investigation includes the effects of source drain resistances which become significant as channel length becomes shorter. In this paper, we evaluate the additional noise caused by three dimensional (3-D) structure of the single fin device and then extended analysis of the multi-fin and multi-fingers structure. The addition of fringe field increases its minimum noise figure and noise resistance of approximately 1 dB and 100 Ω respectively and optimum admittance increases to 5.45 mω at 20 GHz for a device operating under saturation region. Hence, our transformed model plays a significant function in evaluation of accurate noise performance at circuit level.

Key words: FinFET, thermal noise, model



[1]
https://www.arm.com/products/processors/cortex-a/cortex-a72-processor.php
[2]
Guo Yiluan, Wang Guilei, Zhao Chao, et al. Simulation and characterization of stress in FinFETs using novel LKMC and nanobeam diffraction methods. Journal of Semiconductors, 2015, 36(8): 086001 doi: 10.1088/1674-4926/36/8/086001
[3]
Scholten A J, Tiemeijer L F, van Langevelde R, et al. Noise modeling for RF CMOS circuit simulation. IEEE Trans Electron Devices, 2003, 50(3): 618 doi: 10.1109/TED.2003.810480
[4]
Scholten A J, Smit G D J, Pijpere R M T, et al. FinFET compact modelling for analogue and RF applications. IEEE International Electron Devices Meeting, 2010, 2: 8.4.1 http://cn.bing.com/academic/profile?id=2149741487&encoded=0&v=paper_preview&mkt=zh-cn
[5]
Raskin J, Pailloncy G, Lederer D, et al. High-frequency noise performance of 60-nm gate-length FinFETs. IEEE Trans Electron Devices, 2008, 55(10): 2718 doi: 10.1109/TED.2008.2003097
[6]
Wei C, Xiong Y Z, Zhou X. Investigation of low-frequency noise in n-channel FinFETs from weak to strong inversion. IEEE Electron Devices, 2009, 56(11): 2800 doi: 10.1109/TED.2009.2030972
[7]
vKlaassen F M, Prins J. Thermal noise of MOS transistors. Philips Res RTep, 1967, 22: 505 http://cn.bing.com/academic/profile?id=138059704&encoded=0&v=paper_preview&mkt=zh-cn
[8]
Paasschens J C J, Scholten A J, van Langevelde R. Generalizations of the Klaassen-Prins equation for calculating the noise of semiconductor devices. IEEE Trans Electron Devices, 2005, 52(11): 2463 doi: 10.1109/TED.2005.857189
[9]
Shoji M. Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors. IEEE Trans Electron Devices, 1966, ED-13(6): 520 doi: 10.1109/T-ED.1966.15724
[10]
Knoblinger G, Fulde M, Siprak D, et al. Evaluation of FinFET RF building blocks. Proc IEEE International SOI Conference, 2007: 39 http://cn.bing.com/academic/profile?id=2027795658&encoded=0&v=paper_preview&mkt=zh-cn
[11]
Li Z. Compact channel noise models for MOSFETs, deep-submicron. IEEE Trans Electron Devices, 2009, 56(6): 1300 doi: 10.1109/TED.2009.2018160
[12]
Bruncke W C. Noise measurements in field-effect transistors. Proceedings of IEEE (Correspondence), 1963, 51: 378 doi: 10.1109/PROC.1963.1795
[13]
Lu D. Compact models for future generation CMOS. PhD Dissertation, Electrical Engineering and Computer Sciences, University of California, Berkeley, 2011
[14]
Lu N, Kotecha P M, Wachnik R A. Modeling of resistance in FinFET local interconnect. IEEE Circuits and Systems Society, 2015, 62(8): 1899 http://cn.bing.com/academic/profile?id=1537227151&encoded=0&v=paper_preview&mkt=zh-cn
[15]
Huang X, Lee W C, Kuo C, et al. Sub-50 nm p-channel FinFET. IEEE Trans Electron Devices, 2001, 48(5): 880 doi: 10.1109/16.918235
[16]
Chen C H, Deen M J. High frequency noise of MOSFETs I modeling. Solid State Electron, 1998, 42(11): 2069 doi: 10.1016/S0038-1101(98)00192-0
[17]
Arora N. MOSFET modelling for VLSI simulation theory and practice. World Scientific, 2007
[18]
Laìzaro A, Nae B, Iñiguez B, et al. A compact quantum model for fin-shaped field effect transistors valid from dc to high frequency and noise simulations. J Appl Phys, 2008, 103(8): 084507 doi: 10.1063/1.2907720
[19]
Mudanai S, Roy A. Capacitance compact model for ultrathin low-electron-effective-mass materials. IEEE Trans Electron Devices, 2011, 58(12): 4204 doi: 10.1109/TED.2011.2168529
[20]
Shrivastava R. Fitzpatrick K. A simple model for the overlap capacitance of a VLSI MOS device. IEEE Trans Electron Devices, 1982, ED-29(12):1870 http://cn.bing.com/academic/profile?id=1976988595&encoded=0&v=paper_preview&mkt=zh-cn
[21]
Jagadesh M K, Gupta S K, Venkataraman V. Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs. IEEE Trans Electron Devices, 2006, 53(4): 706 doi: 10.1109/TED.2006.870424
[22]
Roy A S, Enz C C, Sallese J M. Noise modeling methodologies in the presence of mobility degradation and their equivalence. IEEE Trans Electron Devices, 2006, 53(2): 348 doi: 10.1109/TED.2005.862703
[23]
Mukherjee C, Maiti C K. Channel thermal noise modeling and high frequency noise parameters of tri-gate FinFETs. 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2013, 2(5): 732 http://cn.bing.com/academic/profile?id=2021830009&encoded=0&v=paper_preview&mkt=zh-cn
[24]
Xu Miao, Yin Huaxiang, Zhu Huilong, et al. Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs. Journal of Semiconductors, 2015, 36(4): 044007 doi: 10.1088/1674-4926/36/4/044007
[25]
Suresh D, Nagarajan K K, Srinivasan R. The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA. Journal of Semiconductors, 2015, 36(4): 045002 doi: 10.1088/1674-4926/36/4/045002
[26]
Wu Weikang, An Xia, Jiang Xiaobo, et al. Line-edge roughness induced single event transient variation in SOI FinFETs. Journal of Semiconductors, 2015, 36(11): 114001 doi: 10.1088/1674-4926/36/11/114001
Fig. 1.  (Color online) (a) 3-D structure and (b) 2-D cross section along A-A' axis of an underlap n-FinFET considered for the potential analysis simulated with TCAD LG=16 nm,H FIN= 30 nm,T Si =8 nm,T SD=20 nm,T OX=1.7 nm.

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Fig. 2.  (Color online) TCAD simulation for fringe electric field at the edge of gate electrode of an underlap n-FinFET cross section considered for the potential analysis simulated with TCAD L G= 16 nm,HFIN= 30 nm,TSI= 8 nm,T SD=40 nm,TOX= 1.7 nm,TG= 40 nm,NF= 2,NFIN=10.

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Fig. 3.  Potential distribution along the fin width for Lun= 7,11,15.5 and 20 nm from (a) source side,(b) drain side. LG = 16 nm and V GS= 0.8 V and VDS= 1 V.

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Fig. 4.  Analytical (line) and simulated (symbols) (a) the charge induced in the channel with and without the fringe field with respect to gate voltage. (b) The effect of gate height on the drain charge due to the presence of the fringe field.

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Fig. 5.  Analytical (line) and simulated (symbols) variation of normalized gate capacitance at gate voltage varying from 0.0 to 0.8 V in steps of 0.1 V for L G=16 nm,H FIN=30 nm,T si=8 nm,T sd=20 nm,Tox=1.7 nm.

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Fig. 6.  (Color online) Simulated (symbols) and Analytical (solid) (a) Variation of RDS with the spacing between fins S and fin width TFIN,(b) effect of the presence of fringe source to drain resistance (Rfr) at VGS= 50 mV with the variation of fin width and underlap length for NFIN= 1.

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Fig. 7.  (Color online) Geometrical dependence of resistance of extended S/D region (with contacts and number of fins) variation of RDS with fin height and extended S/D region with respect to number of fins (a) NFIN=5 and (b) N FIN= 10. L G= 16 nm,TOX= 1.7 nm,NF= 1.

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Fig. 8.  Measured (symbols) and modeled (solid) drain current as a function of frequency for (a) 70 nm[4] and (b) 16 nm FinFET biased at VGS= 1 V and V DS= 1 V.

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Fig. 9.  (Color online) Simulated (symbols) and analytical (solid) results of thermal noise with respect to frequency for LG= 16 nm and N FIN= 5 at VGS= 0.4 V with respect to (a) raised source drain length (Lrsd),(b) variation of gate length (LG),(c) fin height (HFIN),(d) extended source drain thickness (TSD) on the thermal noise.

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Fig. 10.  Simulated (symbols) and analytical (solid lines) trend lines for thermal noise based on various geometrical layouts where (a) gate electrode thickness (TG),(b) variation of gate length (LG),(c) fin height (HFIN).

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Fig. 11.  (Color online) Measured (symbols) and simulated (lines) characteristics of (a) noise resistance Rn,(b) minimum noise figure NFMIN,(c) characteristics of optimum admittance Yopt for L G= 16 nm,HFIN= 30 nm,TFIN=8 nm at VGS= 0.5 V ,VDS= 0.8 V.

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Table 1.   Device dimensions.

Table 2.   Extracted small signal equivalent circuit parameter versus number of fingers and RF noise parameter at 10 GHz for 16 nm gate length finFET,number of fins = 5/finger.
[1]
https://www.arm.com/products/processors/cortex-a/cortex-a72-processor.php
[2]
Guo Yiluan, Wang Guilei, Zhao Chao, et al. Simulation and characterization of stress in FinFETs using novel LKMC and nanobeam diffraction methods. Journal of Semiconductors, 2015, 36(8): 086001 doi: 10.1088/1674-4926/36/8/086001
[3]
Scholten A J, Tiemeijer L F, van Langevelde R, et al. Noise modeling for RF CMOS circuit simulation. IEEE Trans Electron Devices, 2003, 50(3): 618 doi: 10.1109/TED.2003.810480
[4]
Scholten A J, Smit G D J, Pijpere R M T, et al. FinFET compact modelling for analogue and RF applications. IEEE International Electron Devices Meeting, 2010, 2: 8.4.1 http://cn.bing.com/academic/profile?id=2149741487&encoded=0&v=paper_preview&mkt=zh-cn
[5]
Raskin J, Pailloncy G, Lederer D, et al. High-frequency noise performance of 60-nm gate-length FinFETs. IEEE Trans Electron Devices, 2008, 55(10): 2718 doi: 10.1109/TED.2008.2003097
[6]
Wei C, Xiong Y Z, Zhou X. Investigation of low-frequency noise in n-channel FinFETs from weak to strong inversion. IEEE Electron Devices, 2009, 56(11): 2800 doi: 10.1109/TED.2009.2030972
[7]
vKlaassen F M, Prins J. Thermal noise of MOS transistors. Philips Res RTep, 1967, 22: 505 http://cn.bing.com/academic/profile?id=138059704&encoded=0&v=paper_preview&mkt=zh-cn
[8]
Paasschens J C J, Scholten A J, van Langevelde R. Generalizations of the Klaassen-Prins equation for calculating the noise of semiconductor devices. IEEE Trans Electron Devices, 2005, 52(11): 2463 doi: 10.1109/TED.2005.857189
[9]
Shoji M. Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors. IEEE Trans Electron Devices, 1966, ED-13(6): 520 doi: 10.1109/T-ED.1966.15724
[10]
Knoblinger G, Fulde M, Siprak D, et al. Evaluation of FinFET RF building blocks. Proc IEEE International SOI Conference, 2007: 39 http://cn.bing.com/academic/profile?id=2027795658&encoded=0&v=paper_preview&mkt=zh-cn
[11]
Li Z. Compact channel noise models for MOSFETs, deep-submicron. IEEE Trans Electron Devices, 2009, 56(6): 1300 doi: 10.1109/TED.2009.2018160
[12]
Bruncke W C. Noise measurements in field-effect transistors. Proceedings of IEEE (Correspondence), 1963, 51: 378 doi: 10.1109/PROC.1963.1795
[13]
Lu D. Compact models for future generation CMOS. PhD Dissertation, Electrical Engineering and Computer Sciences, University of California, Berkeley, 2011
[14]
Lu N, Kotecha P M, Wachnik R A. Modeling of resistance in FinFET local interconnect. IEEE Circuits and Systems Society, 2015, 62(8): 1899 http://cn.bing.com/academic/profile?id=1537227151&encoded=0&v=paper_preview&mkt=zh-cn
[15]
Huang X, Lee W C, Kuo C, et al. Sub-50 nm p-channel FinFET. IEEE Trans Electron Devices, 2001, 48(5): 880 doi: 10.1109/16.918235
[16]
Chen C H, Deen M J. High frequency noise of MOSFETs I modeling. Solid State Electron, 1998, 42(11): 2069 doi: 10.1016/S0038-1101(98)00192-0
[17]
Arora N. MOSFET modelling for VLSI simulation theory and practice. World Scientific, 2007
[18]
Laìzaro A, Nae B, Iñiguez B, et al. A compact quantum model for fin-shaped field effect transistors valid from dc to high frequency and noise simulations. J Appl Phys, 2008, 103(8): 084507 doi: 10.1063/1.2907720
[19]
Mudanai S, Roy A. Capacitance compact model for ultrathin low-electron-effective-mass materials. IEEE Trans Electron Devices, 2011, 58(12): 4204 doi: 10.1109/TED.2011.2168529
[20]
Shrivastava R. Fitzpatrick K. A simple model for the overlap capacitance of a VLSI MOS device. IEEE Trans Electron Devices, 1982, ED-29(12):1870 http://cn.bing.com/academic/profile?id=1976988595&encoded=0&v=paper_preview&mkt=zh-cn
[21]
Jagadesh M K, Gupta S K, Venkataraman V. Compact modeling of the effects of parasitic internal fringe capacitance on the threshold voltage of high-k gate-dielectric nanoscale SOI MOSFETs. IEEE Trans Electron Devices, 2006, 53(4): 706 doi: 10.1109/TED.2006.870424
[22]
Roy A S, Enz C C, Sallese J M. Noise modeling methodologies in the presence of mobility degradation and their equivalence. IEEE Trans Electron Devices, 2006, 53(2): 348 doi: 10.1109/TED.2005.862703
[23]
Mukherjee C, Maiti C K. Channel thermal noise modeling and high frequency noise parameters of tri-gate FinFETs. 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2013, 2(5): 732 http://cn.bing.com/academic/profile?id=2021830009&encoded=0&v=paper_preview&mkt=zh-cn
[24]
Xu Miao, Yin Huaxiang, Zhu Huilong, et al. Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs. Journal of Semiconductors, 2015, 36(4): 044007 doi: 10.1088/1674-4926/36/4/044007
[25]
Suresh D, Nagarajan K K, Srinivasan R. The impact of process variations on input impedance and mitigation using a circuit technique in FinFET-based LNA. Journal of Semiconductors, 2015, 36(4): 045002 doi: 10.1088/1674-4926/36/4/045002
[26]
Wu Weikang, An Xia, Jiang Xiaobo, et al. Line-edge roughness induced single event transient variation in SOI FinFETs. Journal of Semiconductors, 2015, 36(11): 114001 doi: 10.1088/1674-4926/36/11/114001

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    Received: 14 January 2016 Revised: 08 March 2016 Online: Published: 01 September 2016

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      Article Navigation >  Journal of Semiconductors  > 2016  >  37(9): 094001
      Savitesh Madhulika Sharma, S. Dasgupta, M. V. Kartikeyan. A transformed analytical model for thermal noise of FinFET based on fringing field approximation[J]. Journal of Semiconductors, 2016, 37(9): 094001. doi: 10.1088/1674-4926/37/9/094001 ****S M Sharma, S. Dasgupta, M. V. Kartikeyan. A transformed analytical model for thermal noise of FinFET based on fringing field approximation[J]. J. Semicond., 2016, 37(9): 094001. doi: 10.1088/1674-4926/37/9/094001.
      Citation:
      Savitesh Madhulika Sharma, S. Dasgupta, M. V. Kartikeyan. A transformed analytical model for thermal noise of FinFET based on fringing field approximation[J]. Journal of Semiconductors, 2016, 37(9): 094001. doi: 10.1088/1674-4926/37/9/094001 ****
      S M Sharma, S. Dasgupta, M. V. Kartikeyan. A transformed analytical model for thermal noise of FinFET based on fringing field approximation[J]. J. Semicond., 2016, 37(9): 094001. doi: 10.1088/1674-4926/37/9/094001.
      shu

      A transformed analytical model for thermal noise of FinFET based on fringing field approximation

      DOI: 10.1088/1674-4926/37/9/094001

      • Microelectonics and VLSI Group, Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee 247667, Uttarakhand, India

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      Project supported in part by the All India Council for Technical Education AICTE

      Project supported in part by the All India Council for Technical Education (AICTE)

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      • Corresponding author: kartik@ieee.org
      • Received Date: 2016-01-14
      • Revised Date: 2016-03-08
      • Published Date: 2016-09-01

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