Fig. 1.
Interconnects structure. (a) Interconnects structure of local and intermediate layers.(b) Interconnects structure of top layer
DownLoad:
| Citation: |
Peng Xu, Zhongliang Pan. The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits[J]. Journal of Semiconductors, 2017, 38(9): 095003. doi: 10.1088/1674-4926/38/9/095003
****
P Xu, Z L Pan. The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits[J]. J. Semicond., 2017, 38(9): 095003. doi: 10.1088/1674-4926/38/9/095003.
|
The analytical model for crosstalk noise of current-mode signaling in coupled RLC interconnects of VLSI circuits
DOI: 10.1088/1674-4926/38/9/095003
More Information
-
Abstract
With the continuous advancement of semiconductor technology, the interconnects crosstalk has had a great influence on the performances of VLSI circuits.To date, most of the research about the interconnects of VLSI circuits focus on the voltage-mode signaling (VMS) scheme while the current-mode signaling (CMS) scheme is rarely analyzed.First of all, an equivalent circuit model of two-line coupled interconnects is presented in this paper, which is applicable to both the CMS and VMS schemes.The coupling capacitive and mutual inductive are taken into account in the equivalent circuit model.Secondly, the output noise of CMS and VMS schemes are investigated in the paper according to the decoupling technique andABCD parameter matrix approach at local level, intermediate level and global level, respectively.Moreover, the experimental results show that the CMS interconnects have lesser noise peak, noise width and noise amplitude than the VMS interconnects in the same cases, and the CMS scheme is especially suitable for the global interconnects communication of VLSI circuits.It is found that the results obtained by ABCD parameter matrix approach are in good accordance with the simulation results of the advanced design system. -
References
[1] Heydari P, Pedram M. Capacitive coupling noise in high-speed VLSI circuits. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2005, 24(3):478 doi: 10.1109/TCAD.2004.842798[2] Agarwal K, Sylvester D, Blaauw D. Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans Comput-Aided Des Integr Circuits Syst, 2006, 25(5):892 doi: 10.1109/TCAD.2005.855961[3] Hunagund P V, Kalpana A B. Crosstalk noise modeling for RC and RLC interconnects in deep submicron VLSI circuits. J Comput, 2010, 2(4):60 https://arxiv.org/pdf/1004.4458[4] Kumar V R, Kaushik B K, Patnaik A. Crosstalk noise modeling of multiwall carbon nanotube (MWCNT) interconnects using finite-difference time-domain (FDTD) technique. Microelectron Reliab, 2015, 55(1):155 doi: 10.1016/j.microrel.2014.09.001[5] Liu X, Ma G, Shao J, et al. Interconnect crosstalk noise evaluation in deep-submicron technologies. Microelectron Reliab, 2009, 49(2):170 doi: 10.1016/j.microrel.2008.11.013[6] Hunagund P V, Kalpana A B. Analytical noise modeling for shielding to reduce crosstalk noise in on-chip interconnects. Int J Comput Sci Network Security, 2010[7] Singh S, Verma S. Reduction of crosstalk noise and delay in VLSI interconnects using Schmitt trigger as a buffer and wire sizing. Adv Comput Inform Technol, 2013, 178:677 doi: 10.1007/978-3-642-31600-5[8] Tuuna S, Nigussie E, Isoaho J, et al. Modeling of energy dissipation in RLC current-mode signaling. IEEE Trans Very Large Scale Integr Syst, 2012, 20(6):1146 doi: 10.1109/TVLSI.2011.2140345[9] Agrawal Y, Chandel R, Dhiman R. Design and analysis of efficient multilevel receiver for current mode interconnect system. IEEE Students Conference Electrical Electronics and Computer Sciences, 2014:1 http://ieeexplore.ieee.org/document/6804483/[10] Dave M, Jain M, Baghini M S, et al. A variation tolerant current mode signaling scheme for on-chip interconnect. IEEE Trans Very Large Scale Integr Syst, 2013, 21(2):342 doi: 10.1109/TVLSI.2012.2185835[11] Wang T, Yuan F. A new current-mode incremental signaling scheme with applications to Gb/s parallel links. IEEE Trans Circuits Syst, 2007, 54(2):255 doi: 10.1109/TCSI.2006.885977[12] Jose A P, Patounakis G, Shepard K L. Pulsed current-mode signaling for nearly speed-of-light intrachip communication. IEEE J Solid-State Circuits, 2006, 41(4):772 doi: 10.1109/JSSC.2006.870922[13] Agrawal Y, Chandel R. Crosstalk analysis of current-mode signaling-coupled RLC interconnects using FDTD technique. IETE Tech Rev, 2016, 33(2):148 doi: 10.1080/02564602.2015.1056258[14] Predictive technology model. http://ptm.asu.edu/[15] Kim T, Kim D, Lee J A, et al. Compact models for signal transient and crosstalk noise of coupled RLC interconnect lines with ramp inputs. IEEE International Symposium on Electronic Design, Test & Applications, 2008:205 doi: 10.1109/DELTA.2008.7[16] Zhang J, Friedman E G. Decoupling technique and crosstalk analysis for coupled RLC interconnects. Proceedings of the 2004 International Symposium on IEEE Circuits and Systems, 2004:521 http://ieeexplore.ieee.org/document/1329323/[17] Banerjee K, Mehrotra A. Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling. IEEE Symposium on VLSI Circuits, 2001:195 http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.23.8151[18] Sahoo M, Rahaman H. Modeling of crosstalk induced effects in copper-based nanointerconnects:an ABCD parameter matrixbased approach. J Circuits Syst Comput, 2015, 24(2):1 doi: 10.1142/S0218126615400071[19] Zhang J, Friedman G. Decoupling technique and crosstalk analysis for coupled RLC interconnects. Proceedings of the 2004 International Symposium on Circuits and Systems, 2004:521 http://ieeexplore.ieee.org/document/1329323/[20] Sahoo M, Ghosal P, Rahaman H. Performance modeling and analysis of carbon nanotube bundles for future VLSI circuit applications. J Comput Electron, 2014, 13(3):673 doi: 10.1007/s10825-014-0587-7[21] Semiconductor Industry Association 2005 International Technology Roadmap for Semiconductors 2005(ITRS 2005) -
Proportional views
