J. Semicond. > 2018, Volume 39 > Issue 2 > 025002
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SEMICONDUCTOR INTEGRATED CIRCUITS

A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation

Vipul Bhatnagar1, Pradeep Kumar1, Neeta Pandey2 and Sujata Pandey1,

+ Author Affiliations

 Corresponding author: Sujata Pandey, Email: spandey11@gmail.com

DOI: 10.1088/1674-4926/39/2/025002

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Abstract: This paper presents a new dual Vt 8T SRAM cell having single bit-line read and write, in addition to Write Assist and Read Isolation (WARI). Also a faster write back scheme is proposed for the half selected cells. A high Vt device is used for interrupting the supply to one of the inverters for weakening the feedback loop for assisted write. The proposed cell provides an improved read static noise margin (RSNM) due to the bit-line isolation during the read. Static noise margins for data read (RSNM), write (WSNM), read delay, write delay, data retention voltage (DRV), leakage and average powers have been calculated. The proposed cell was found to operate properly at a supply voltage as small as 0.41 V. A new write back scheme has been suggested for half-selected cells, which uses a single NMOS access device and provides reduced delay, pulse timing hardware requirements and power consumption. The proposed new WARI 8T cell shows better performance in terms of easier write, improved read noise margin, reduced leakage power, and less delay as compared to the existing schemes that have been available so far. It was also observed that with proper adjustment of the cell ratio the supply voltage can further be reduced to 0.2 V.

Key words: dual Vt, disturb free, write assist, read isolation, half selected cells



[1]
Mooney V. Research trends in hardware/software codesign of embedded operating systems for FPGAs. FPGA Worlds, 2007
[2]
Chandrakasan A P, Daly D C, Finchelstein D F. Technologies for ultradynamic voltage scaling. Proc IEEE, 2010, 98(2): 191 doi: 10.1109/JPROC.2009.2033621
[3]
Zhang K, Hamzaoglu F, Wang Y. Low-power SRAMs in nanoscale CMOS technologies. IEEE Trans Electron Devices, 2008, 55(1): 145 doi: 10.1109/TED.2007.911356
[4]
Gottscho, Banaiyanmofrad A, Dutt N, et al. DPCS: dynamic power/capacity scaling for SRAM caches in the nanoscale era. ACM Trans Architect Code Optim, 2015, 12(3): 27
[5]
Fan M L, Wu Y S, Hu V H, et al. Investigation of cell stability and write ability of FinFET subthreshold SRAM using analytical SNM model. IEEE Trans Electron Devices, 2010, 57(6): 1375 doi: 10.1109/TED.2010.2046988
[6]
Bansal A, Mukhopadhyay S, Roy K. Device-optimization technique for robust and low-power FinFET SRAM design in nanoscale era. IEEE Trans Electron Devices, 2007, 54(6): 1409 doi: 10.1109/TED.2007.895879
[7]
Rabaey J M. Low power design essentials. NY: Springer-Verlag, 2009
[8]
Islam S, Hasan M. Variability aware low leakage reliable SRAM cell design technique. Microelectron Reliab, 2012, 52(6): 1247 doi: 10.1016/j.microrel.2012.01.003
[9]
Pasandi G, Fakhraie S M. A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS. Proc 21st ICEE , 2013: 1
[10]
Aly R, Bayoumi M. Low-power cache design using 7T SRAM cell. IEEE Trans Circuits Syst II, 2007, 54(4): 318 doi: 10.1109/TCSII.2006.877276
[11]
Zhai B, Hanson S, Blaauw D, et al. A variation-tolerant sub-200 mV 6-T subthreshold SRAM. IEEE J Solid-State Circuits, 2008, 43(10): 2338 doi: 10.1109/JSSC.2008.2001903
[12]
Wen L, Li Z T, Li Y. Single-ended, robust 8T SRAM cell for low-voltage operation. Microelectron J, 2013, 44(8): 718 doi: 10.1016/j.mejo.2013.04.007
[13]
Gupta P, Gupta N, Asati A. Leakage immune modified pass transistor based 8T SRAM cell in subthreshold Region. Int J Reconfig Comput, 2015, 2015: 749816
[14]
Sharifkhani M, Sachdev M. Segmented virtual ground architecture for low-power embedded SRAM. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2007, 15(2): 196 doi: 10.1109/TVLSI.2007.893584
[15]
Kulkarni K K, Roy K. A 160 mV robust Schmitt trigger based subthreshold SRAM. IEEE J Solid-State Circuits, 2007, 42(10): 2303 doi: 10.1109/JSSC.2007.897148
[16]
Islam A, Hasan M. Leakage characterization of 10T SRAM cell. IEEE Trans Electron Devices, 2012, 59(3): 631 doi: 10.1109/TED.2011.2181387
[17]
Liu Z, Kursun V. Characterization of a novel nine-transistor SRAM cell. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2008, 16(4): 488 doi: 10.1109/TVLSI.2007.915499
[18]
Wen L, Duan Z K, Li Y, et al. Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability. Microelectron J, 2014, 45(6): 815 doi: 10.1016/j.mejo.2014.02.020
[19]
Wang B, Zhou J, Kim T T H. SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS. Microelectron J, 2015, 46(3): 265 doi: 10.1016/j.mejo.2014.12.003
[20]
Morifuji E, Patil D, Horowitz, et al. Power optimization for SRAM and its scaling. IEEE Trans Electron Devices, 2007, 54(4): 715 doi: 10.1109/TED.2007.891869
[21]
Roy K, Mak T M, Cheng K T. Test consideration for nanoscale scale CMOS circuits. IEEE Des Test J, 2006, 23: 128 doi: 10.1109/MDT.2006.52
[22]
Roy K, Mukhopadhyay S, Mahmoodi-Meimand H. Leakage current mechanisms and leakage reduction techniques in deep-submicronmeter CMOS circuits. Proc IEEE, 2003, 91(2): 305 doi: 10.1109/JPROC.2002.808156
[23]
Lee D W, Kwong W, Blaauw S, et al. Analysis and minimization techniques for total leakage considering gate oxide leakage. 40th Annual Design and Automation Conference, 2003: 175
[24]
Kulkarni J, Kim K, Roy K. A 160 mV robust Schmitt trigger based subthreshold SRAM. IEEE J Solid-State Circuits, 2007, 42(10): 2303 doi: 10.1109/JSSC.2007.897148
[25]
Wang J, Singhee A, Rutenbar R, et al. Statistical modeling for minimum standby supply voltage of a full SRAM array. 33rd Proc ESSCIRC, 2007: 400
[26]
Yashimoto M, Anami K, Shinohara H, et al. A divided word line structure in the static RAM and its application to a 64K full CMOS SRAM. IEEE J Solid-State Circuits, 1983, 18(5): 479 doi: 10.1109/JSSC.1983.1051981
[27]
Honda K, Miyaji K, Tanakamaru S, et al. Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. Proc IEEE CICC, 2010: 1
[28]
Pasandi G, Fakhraie S M. An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs. IEEE Trans Electron Devices, 2014, 61(7): 2357 doi: 10.1109/TED.2014.2321295
[29]
Kim T H, Liu J, Keane J, et al. A 0.2 V, 480 Kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing. IEEE J Solid-State Circuits, 2008, 43(2): 518 doi: 10.1109/JSSC.2007.914328
Fig. 1.  (a) 6T cell. (b) WRE 8T cell. (c) LP 10T Cell. (d) Conventional 8T cell. (e) Proposed WARI 8T cell.

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Fig. 2.  Comparison of (a) 6T and (b) the proposed cell.

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Fig. 3.  Waveforms of nodal voltages during write operation of WARI 8T and 6T.

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Fig. 4.  Implementation of the proposed cell.

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Fig. 6.  Variation of WSNM with supply voltage.

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Fig. 7.  Right inverter sizing versus RSNM, WSNM and HSNM at 0.4 V supply.

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Fig. 8.  High Vt supply interrupt device width versus SNM.

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Fig. 9.  WARI 8T cell write operation with capacitive load.

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Fig. 10.  Variation of write delay with write bit line capacitance.

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Fig. 11.  Variation of WSNM with write access device width.

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Fig. 12.  Variation of leakage power with supply voltage.

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Fig. 13.  Variation of RSNM with supply voltage.

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Fig. 14.  Variation of RSNM with read access device width.

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Fig. 15.  Variation of write power with supply voltage.

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Fig. 16.  Variation of read power with supply voltage.

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Fig. 18.  (Color online) Comparison of relative WSNM, RSNM, HSNM and leakage power (in 10 μW) for 6T, WRE8T, conventional 8T, LP10T and proposed WARI 8T.

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Fig. 19.  (Color online) RSNM of WARI 8T cell parametric sweep for supply voltage 0.4 to 1 V, temperature 23 to 73 °C cell pull-up ratio 1 to 5.

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Fig. 20.  (Color online) WSNM of WARI 8T cell parametric sweep for supply voltage 0.4 to 1 V, temperature 23 to 73 °C, cell pull-up ratio 1 to 5.

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Fig. 21.  Write delay versus write access device sizing variation of the proposed WARI 8T cell.

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Fig. 22.  Read delay versus supply voltage variation of the proposed WARI 8T cell.

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Fig. 5.  (Color online) Transient analysis of WARI 8T cell.

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Fig. 17.  (Color online) Read power, write power and leakage power.

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Fig. 23.  Write margin of the proposed 8T cell for process corners.

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Table 1.   WSNM, RSNM, HSNM, write power, read power, leakage power, write delay and read delay at 0.4 V supply.

Parameter WARI 8T WRE 8T LP10T 6T
WSNM (V) 0.81 0.34 0.15 0.20
RSNM (V) 0.15 0.14 0.12 0.12
HSNM (V) 0.20 0.28 0.14 0.21
Write power (μW) 0.02 0.43 0.11 0.82
Read power (μW) 1.83 × 10−5 0.40 0.14 0.82
Leakage power(μW) 0.02 0.44 0.53 0.82
Write delay(ps) 17 39 79 7
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Table 2.   Write-margin and write-time for proposed BNBL WA 11T scheme for FF, FS, SF and SS process corners.

Process corner FF FS SF SS
Write-margin (mV) 77 69 48 26
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[1]
Mooney V. Research trends in hardware/software codesign of embedded operating systems for FPGAs. FPGA Worlds, 2007
[2]
Chandrakasan A P, Daly D C, Finchelstein D F. Technologies for ultradynamic voltage scaling. Proc IEEE, 2010, 98(2): 191 doi: 10.1109/JPROC.2009.2033621
[3]
Zhang K, Hamzaoglu F, Wang Y. Low-power SRAMs in nanoscale CMOS technologies. IEEE Trans Electron Devices, 2008, 55(1): 145 doi: 10.1109/TED.2007.911356
[4]
Gottscho, Banaiyanmofrad A, Dutt N, et al. DPCS: dynamic power/capacity scaling for SRAM caches in the nanoscale era. ACM Trans Architect Code Optim, 2015, 12(3): 27
[5]
Fan M L, Wu Y S, Hu V H, et al. Investigation of cell stability and write ability of FinFET subthreshold SRAM using analytical SNM model. IEEE Trans Electron Devices, 2010, 57(6): 1375 doi: 10.1109/TED.2010.2046988
[6]
Bansal A, Mukhopadhyay S, Roy K. Device-optimization technique for robust and low-power FinFET SRAM design in nanoscale era. IEEE Trans Electron Devices, 2007, 54(6): 1409 doi: 10.1109/TED.2007.895879
[7]
Rabaey J M. Low power design essentials. NY: Springer-Verlag, 2009
[8]
Islam S, Hasan M. Variability aware low leakage reliable SRAM cell design technique. Microelectron Reliab, 2012, 52(6): 1247 doi: 10.1016/j.microrel.2012.01.003
[9]
Pasandi G, Fakhraie S M. A new sub-threshold 7T SRAM cell design with capability of bit-interleaving in 90 nm CMOS. Proc 21st ICEE , 2013: 1
[10]
Aly R, Bayoumi M. Low-power cache design using 7T SRAM cell. IEEE Trans Circuits Syst II, 2007, 54(4): 318 doi: 10.1109/TCSII.2006.877276
[11]
Zhai B, Hanson S, Blaauw D, et al. A variation-tolerant sub-200 mV 6-T subthreshold SRAM. IEEE J Solid-State Circuits, 2008, 43(10): 2338 doi: 10.1109/JSSC.2008.2001903
[12]
Wen L, Li Z T, Li Y. Single-ended, robust 8T SRAM cell for low-voltage operation. Microelectron J, 2013, 44(8): 718 doi: 10.1016/j.mejo.2013.04.007
[13]
Gupta P, Gupta N, Asati A. Leakage immune modified pass transistor based 8T SRAM cell in subthreshold Region. Int J Reconfig Comput, 2015, 2015: 749816
[14]
Sharifkhani M, Sachdev M. Segmented virtual ground architecture for low-power embedded SRAM. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2007, 15(2): 196 doi: 10.1109/TVLSI.2007.893584
[15]
Kulkarni K K, Roy K. A 160 mV robust Schmitt trigger based subthreshold SRAM. IEEE J Solid-State Circuits, 2007, 42(10): 2303 doi: 10.1109/JSSC.2007.897148
[16]
Islam A, Hasan M. Leakage characterization of 10T SRAM cell. IEEE Trans Electron Devices, 2012, 59(3): 631 doi: 10.1109/TED.2011.2181387
[17]
Liu Z, Kursun V. Characterization of a novel nine-transistor SRAM cell. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2008, 16(4): 488 doi: 10.1109/TVLSI.2007.915499
[18]
Wen L, Duan Z K, Li Y, et al. Analysis of a read disturb-free 9T SRAM cell with bit-interleaving capability. Microelectron J, 2014, 45(6): 815 doi: 10.1016/j.mejo.2014.02.020
[19]
Wang B, Zhou J, Kim T T H. SRAM devices and circuits optimization toward energy efficiency in multi-Vth CMOS. Microelectron J, 2015, 46(3): 265 doi: 10.1016/j.mejo.2014.12.003
[20]
Morifuji E, Patil D, Horowitz, et al. Power optimization for SRAM and its scaling. IEEE Trans Electron Devices, 2007, 54(4): 715 doi: 10.1109/TED.2007.891869
[21]
Roy K, Mak T M, Cheng K T. Test consideration for nanoscale scale CMOS circuits. IEEE Des Test J, 2006, 23: 128 doi: 10.1109/MDT.2006.52
[22]
Roy K, Mukhopadhyay S, Mahmoodi-Meimand H. Leakage current mechanisms and leakage reduction techniques in deep-submicronmeter CMOS circuits. Proc IEEE, 2003, 91(2): 305 doi: 10.1109/JPROC.2002.808156
[23]
Lee D W, Kwong W, Blaauw S, et al. Analysis and minimization techniques for total leakage considering gate oxide leakage. 40th Annual Design and Automation Conference, 2003: 175
[24]
Kulkarni J, Kim K, Roy K. A 160 mV robust Schmitt trigger based subthreshold SRAM. IEEE J Solid-State Circuits, 2007, 42(10): 2303 doi: 10.1109/JSSC.2007.897148
[25]
Wang J, Singhee A, Rutenbar R, et al. Statistical modeling for minimum standby supply voltage of a full SRAM array. 33rd Proc ESSCIRC, 2007: 400
[26]
Yashimoto M, Anami K, Shinohara H, et al. A divided word line structure in the static RAM and its application to a 64K full CMOS SRAM. IEEE J Solid-State Circuits, 1983, 18(5): 479 doi: 10.1109/JSSC.1983.1051981
[27]
Honda K, Miyaji K, Tanakamaru S, et al. Elimination of half select disturb in 8T-SRAM by local injected electron asymmetric pass gate transistor. Proc IEEE CICC, 2010: 1
[28]
Pasandi G, Fakhraie S M. An 8T low-voltage and low-leakage half-selection disturb-free SRAM using bulk-CMOS and FinFETs. IEEE Trans Electron Devices, 2014, 61(7): 2357 doi: 10.1109/TED.2014.2321295
[29]
Kim T H, Liu J, Keane J, et al. A 0.2 V, 480 Kb subthreshold SRAM with 1 k cells per bitline for ultra-low-voltage computing. IEEE J Solid-State Circuits, 2008, 43(2): 518 doi: 10.1109/JSSC.2007.914328

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    Received: 22 March 2017 Revised: 16 August 2017 Online: Uncorrected proof: 24 January 2018Accepted Manuscript: 02 February 2018Published: 02 February 2018

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      Article Navigation >  Journal of Semiconductors  > 2018  >  39(2): 025002
      Vipul Bhatnagar, Pradeep Kumar, Neeta Pandey, Sujata Pandey. A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation[J]. Journal of Semiconductors, 2018, 39(2): 025002. doi: 10.1088/1674-4926/39/2/025002 ****V Bhatnagar, P Kumar, Neeta Pandey, Sujata Pandey. A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation[J]. J. Semicond., 2018, 39(2): 025002. doi: 10.1088/1674-4926/39/2/025002.
      Citation:
      Vipul Bhatnagar, Pradeep Kumar, Neeta Pandey, Sujata Pandey. A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation[J]. Journal of Semiconductors, 2018, 39(2): 025002. doi: 10.1088/1674-4926/39/2/025002 ****
      V Bhatnagar, P Kumar, Neeta Pandey, Sujata Pandey. A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation[J]. J. Semicond., 2018, 39(2): 025002. doi: 10.1088/1674-4926/39/2/025002.
      shu

      A dual Vt disturb-free subthreshold SRAM with write-assist and read isolation

      DOI: 10.1088/1674-4926/39/2/025002
      • 1.

        Department of Electronics and Communication Engineering, Amity University Uttar Pradesh, Noida, India

      • 2.

        Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India

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      • Corresponding author: Email: spandey11@gmail.com
      • Received Date: 2017-03-22
      • Revised Date: 2017-08-16
        • Available Online: 2018-02-01
      • Published Date: 2018-02-01

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