Fig. 1.
(Color online) A MOPNS under the influence of small negative voltage applied to its gate.
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| Citation: |
H. Zandipour, M. Madani. Design, modelling, and simulation of a floating gate transistor with a novel security feature[J]. Journal of Semiconductors, 2020, 41(10): 102105. doi: 10.1088/1674-4926/41/10/102105
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H Zandipour, M Madani, Design, modelling, and simulation of a floating gate transistor with a novel security feature[J]. J. Semicond., 2020, 41(10): 102105. doi: 10.1088/1674-4926/41/10/102105.
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Design, modelling, and simulation of a floating gate transistor with a novel security feature
DOI: 10.1088/1674-4926/41/10/102105
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Abstract
This study proposes a new generation of floating gate transistors (FGT) with a novel built-in security feature. The new device has applications in guarding the IC chips against the current reverse engineering techniques, including scanning capacitance microscopy (SCM). The SCM measures the change in the C–V characteristic of the device as a result of placing a minute amount of charge on the floating gate, even in nano-meter scales. The proposed design only adds a simple processing step to the conventional FGT by adding an oppositely doped implanted layer to the substrate. This new structure was first analyzed theoretically and then a two-dimensional model was extracted to represent its C–V characteristic. Furthermore, this model was verified with a simulation. In addition, the C–V characteristics relevant to the SCM measurement of both conventional and the new designed FGT were compared to discuss the effectiveness of the added layer in masking the state of the transistor. The effect of change in doping concentration of the implanted layer on the C–V characteristics was also investigated. Finally, the feasibility of the proposed design was examined by comparing its I–V characteristics with the traditional FGT. -
References
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