Fig. 1.
(Color online) Noise modulation under different modulation orders.
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Guiping Cao, Ning Dong. An 18-bit sigma –delta switched-capacitor modulator using 4-order single-loop CIFB architecture[J]. Journal of Semiconductors, 2020, 41(6): 062404. doi: 10.1088/1674-4926/41/6/062404
G P Cao, N Dong, An 18-bit sigma –delta switched-capacitor modulator using 4-order single-loop CIFB architecture[J]. J. Semicond., 2020, 41(6): 062404. doi: 10.1088/1674-4926/41/6/062404.
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An 18-bit sigma –delta switched-capacitor modulator using 4-order single-loop CIFB architecture
doi: 10.1088/1674-4926/41/6/062404
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Abstract
Oversampling sigma–delta (Σ–Δ) analog-to-digital converters (ADCs) are currently one of the most widely used architectures for high-resolution ADCs. The rapid development of integrated circuit manufacturing processes has allowed the realization of a high resolution in exchange for speed. Structurally, the Σ–Δ ADC is divided into two parts: a front-end analog modulator and a back-end digital filter. The performance of the front-end analog modulator has a marked influence on the entire Σ–Δ ADC system. In this paper, a 4-order single-loop switched-capacitor modulator with a CIFB (cascade-of-integrators feed-back) structure is proposed. Based on the chosen modulator architecture, the ASIC circuit is implemented using a chartered 0.35 μm CMOS process with a chip area of 1.72 × 0.75 mm2. The chip operates with a 3.3-V power supply and a power dissipation of 22 mW. According to the results, the performance of the designed modulator has been improved compared with a mature industrial chip and the effective number of bits (ENOB) was almost 18-bit. -
References
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