Citation: |
Genquan Han, Yue Hao. Design technology co-optimization towards sub-3 nm technology nodes[J]. Journal of Semiconductors, 2021, 42(2): 020301. doi: 10.1088/1674-4926/42/2/020301
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G Q Han, Y Hao, Design technology co-optimization towards sub-3 nm technology nodes[J]. J. Semicond., 2021, 42(2): 020301. doi: 10.1088/1674-4926/42/2/020301.
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Design technology co-optimization towards sub-3 nm technology nodes
DOI: 10.1088/1674-4926/42/2/020301
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References
[1] Bae G, Bae D I, Kang M, et al. 3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications. 2018 IEEE International Electron Devices Meeting (IEDM), 2018, 28[2] Weckx P, Ryckaert J, Litta E D, et al. Novel forksheet device architecture as ultimate logic scaling device towards 2nm. 2019 IEEE International Electron Devices Meeting (IEDM), 2019, 36[3] Ryckaert J, Schuddinck P, Weckx P, et al. The complementary FET (CFET) for CMOS scaling beyond N3. 2018 IEEE Symposium on VLSI Technology, 2018, 141[4] Liu M, Scholz S, Mertens K, et al. First demonstration of vertical Ge0.92Sn0.08/Ge and Ge GAA nanowire nMOSFETs with low SS of 66 mV/dec and small DIBL of 35 mV/V. 2019 IEEE International Electron Devices Meeting (IEDM), 2019, 29[5] Hills G, Lau C, Wright A, et al. Modern microprocessor built from complementary carbon nanotube transistors. Nature, 2019, 572(7771), 595 doi: 10.1038/s41586-019-1493-8 -
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