J. Semicond. > 2023, Volume 44 > Issue 4 > 040203
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RESEARCH HIGHLIGHTS

Digital-intensive RFIC design techniques for transmitters in ISSCC 2023

Yun Yin and Hongtao Xu

+ Author Affiliations

 Corresponding author: Yun Yin, yiny@fudan.edu.cn; Hongtao Xu, hongtao@fudan.edu.cn

DOI: 10.1088/1674-4926/44/4/040203

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Sub-6 GHz multi-standard wireless communication and millimeter-wave (mm-wave) wireless transmission provide users with multi-functionality and unprecedented wireless connectivity. With CMOS process scaling down, system-on-chip (SoC) implementation of wireless systems along with RFIC functionality is highly desirable for low cost and small form-factor. The digital transceiver architecture aligns with Moore’s law to provide compact die area, better interface to digital backend and higher efficiency due to the faster switching nature of core devices[1-28].

The digital PA (DPA) plays a dominant role in digital transmitters (DTXs), which performs digital-to-analog conversion, frequency up-conversion and power amplification all-in-one. Since modern wireless standards widely adopt orthogonal frequency division multiplexing (OFDM) and high-order quadrature amplitude modulation (QAM) to increase throughput and spectral utilization, it requires the DPA to achieve high output power (e.g., >30 dBm), high linearity and high efficiency especially at back-off power levels.

Relevant intensive researches at sub-6 GHz have been directed toward class-D based switched-capacitor PAs, which are more amenable to CMOS scaling and have good linearity and efficiency due to fast low-loss switches and precise capacitor matching. In ISSCC 2023, two works on sub-6 GHz DTX/DPA came from Fudan University[5, 7]. In Ref. [5], a single-channel quadrature DTX supporting multi-mode multi-band NB-IoT/BLE applications is proposed. It introduces a sliding digital-IF quadrature architecture to replace the fractional up-sampling module and achieve pure output spectrum. Besides, a compact wideband Doherty DPA with IQ cell-sharing is implemented to enhance output power and back-off efficiency. This multi-mode NB-IoT/BLE DTX chip achieves Watt-level peak power with >40% system efficiency while occupying only 0.79 mm2 core area, which is well-fitting low-cost IoT applications.

In Ref. [7], a 4.1 W quadrature DPA with 33.6% peak PAE in 28 nm bulk CMOS is presented. It introduces the cascode and 8-way differential power-combining techniques to enhance output power by 16 times. Besides, the IQ cell-sharing and transformer-based Doherty techniques are introduced to further enhance output power by 2 times and achieve 12 efficiency peaks in the complex domain. Powered by 1.1 V/2.2 V supply voltages and packaged in an QFN format, this DPA chip achieves 4.1 W peak power and close-to-Watt-level average power with competitive efficiency performance even compared with polar DPAs, which is very attractive for compact and fast system integration in 5G applications.

mm-wave wireless transmission with multi-Gb/s data rate also demands wideband signal processing, high system efficiency and high output power for large coverage. In ISSCC 2023, a 71–89 GHz DPA came from University of Electronic Science and Technology of China[26]. In Ref. [26], the double-edge-triggered technique is proposed to double the signal bandwidth with limited sampling clock. Besides, the LO leakage suppression and balance-compensated power-combining techniques are introduced to enhance linearity and efficiency. Implemented in 40 nm CMOS, this mm-wave DPA obtains 12 Gb/s high-speed data rate, 20.5 dBm peak output power and 20.4% system efficiency, which is quite competitive for E-band wireless applications.

Moreover, two DTX works are implemented for FMCW chirps from Infineon Technologies[27] and low-power cryogenic controller IC design from Tsinghua University[28]. In Ref. [27], accurate frequency modulation of a direct digital frequency synthesizer is combined with the RFDAC to generate precise wide-bandwidth frequency ramps, which achieves 4 GHz modulation bandwidth with <3 dB power variation. In Ref. [28], a polar architecture with DPA-based amplitude modulation and injection-locking LO based phase modulation is proposed. Its power consumption is 13.7 mW per qubit under active control and the average chip area per channel is only 0.9 mm2.

In Table 1, various DTX/DPAs operating from sub-6 GHz to mm-wave bands with multi-mode multi-band, output power, good efficiency, linearity and bandwidth have been summarized. With these advanced metrics, the digital RF front-end will be a good candidate for modern and further wireless applications.

Table 1.  Performance metrics of DTX/DPAs at sub-6 GHz and mm-wave bands (2019–2023).
Performance metricSystem effectArchitecture/design technique
Multi-mode
Multi-band		Flexibility and low costQuadrature/polar dual-mode reconfigurable[2]; wideband DTC/DPC-based phase modulation[3, 4]; sliding digital-IF quadrature DTX[5]
Output powerCommunication rangePower combining with stacked device[6, 7]; multiphase beamforming[8]; IQ cell-sharing[9]
Power efficiencyBattery lifeTime-interleaving Doherty class-G[10]; switched transformer[11]; multi-subharmonic switching[12]; class-G[13, 14]; Doherty[15]; complex-domain Doherty [9]; hybrid Doherty and impedance boosting[16, 17]; class-G Doherty[18]
LinearityData error rate and modulation typePhase nonlinearity compensation[15]; switch impedance linearization and code mapping[19]; ADC background correction[20]; tri-phasing modulation[21]
Signal bandwidthData rate and license costDual-band matching[22, 23]; edge combining class-D[24]; mm-wave power-DAC [25]; doubled-edge- triggered RFDAC[26]
DownLoad: CSV  | Show Table


[1]
Chan C H, Cheng L, Deng W, et al. Trending IC design directions in 2022. J Semicond, 2022, 43, 071401 doi: 10.1088/1674-4926/43/7/071401
[2]
Yin Y, Zhu Y T, Xiong L, et al. A compact transformer-combined polar/quadrature reconfigurable digital power amplifier in 28-nm logic LP CMOS. IEEE J Solid State Circuits, 2019, 54, 709 doi: 10.1109/JSSC.2018.2878831
[3]
Hu C X, Yin Y, Li T, et al. A fully-integrated wideband digital polar transmitter with 11-bit digital-to-phase converter in 40nm CMOS. IEEE J Solid State Circuits, 2023, 58, 462 doi: 10.1109/JSSC.2022.3192281
[4]
Palaskas Y, Madoglio P, Angel J, et al. A cellular multiband DTC-based digital polar transmitter with −153-dBc/Hz noise in 14-nm FinFET. IEEE J Solid-State Circuits, 2020, 55, 1830 doi: 10.1109/JSSC.2020.2987698
[5]
Hu C, Zheng D, Yin Y, et al. A 0.7-2.5GHz sliding digital-IF quadrature digital transmitter achieving >40% system efficiency for multi-mode NB-IoT/BLE applications. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 472
[6]
Yang B Z, Qian H J, Wang T Y, et al. A CMOS wideband watt-level 4096-QAM digital power amplifier using reconfigurable power-combining transformer. IEEE J Solid State Circuits, 2022, 58, 357 doi: 10.1109/JSSC.2022.3191975
[7]
Li J, Yin Y, Chen H, et al. A 4.1W quadrature doherty digital power amplifier with 33.6% peak pae in 28nm bulk CMOS. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 370
[8]
Bai Z D, Yuan W, Azam A, et al. 4.3 A multiphase interpolating digital power amplifier for TX beamforming in 65nm CMOS. 2019 IEEE International Solid-State Circuits Conference (ISSCC), 2019, 78 doi: 10.1109/ISSCC.2019.8662430
[9]
Zheng D Y, Yin Y, Zhu Y T, et al. 24.5 A 15b quadrature digital power amplifier with transformer-based complex-domain power-efficiency enhancement. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020, 370 doi: 10.1109/ISSCC19947.2020.9062959
[10]
Yoo S W, Hung S C, Yoo S M. 24.4 A watt-level multimode multi-efficiency-peak digital polar power amplifier with linear single-supply class-G technique. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020, 368 doi: 10.1109/ISSCC19947.2020.9063069
[11]
Xiong L, Li T, Yin Y, et al. A broadband switched-transformer digital power amplifier for deep back-off efficiency enhancement. 2019 IEEE International Solid-State Circuits Conference (ISSCC), 2019, 76 doi: 10.1109/JSSC.2020.3005798
[12]
Zhang A Y, Chen M S W. A subharmonic switching digital power amplifier for power back-off efficiency enhancement. IEEE J Solid State Circuits, 2019, 54, 1017 doi: 10.1109/JSSC.2019.2893534
[13]
Yoo S W, Hung S C, Yoo S M. A watt-level quadrature class-G switched-capacitor power amplifier with linearization techniques. IEEE J Solid State Circuits, 2019, 54, 1274 doi: 10.1109/JSSC.2019.2904209
[14]
Bechthum E, El Soussi M, Dijkhuis J F, et al. A CMOS polar class-G switched-capacitor PA with a single high-current supply, for LTE NB-IoT and eMTC. IEEE J Solid State Circuits, 2019, 54, 1941 doi: 10.1109/JSSC.2019.2910407
[15]
Jung D, Li S S, Park J S, et al. A CMOS 1.2-V hybrid current- and voltage-mode three-way digital Doherty PA with built-In phase nonlinearity compensation. IEEE J Solid State Circuits, 2020, 55, 525 doi: 10.1109/JSSC.2019.2953832
[16]
Qian H J, Yang B Z, Zhou J, et al. A quadrature digital power amplifier with hybrid Doherty and impedance boosting for complex domain power back-off efficiency enhancement. IEEE J Solid State Circuits, 2021, 56, 1487 doi: 10.1109/JSSC.2021.3059113
[17]
Yang B Z, Qian H J, Luo X. Quadrature switched/floated capacitor power amplifier with reconfigurable self-coupling canceling transformer for deep back-off efficiency enhancement. IEEE J Solid State Circuits, 2021, 56, 3715 doi: 10.1109/JSSC.2021.3113511
[18]
Hung S C, Yoo S W, Yoo S M. A quadrature class-G complex-domain Doherty digital power amplifier. IEEE J Solid State Circuits, 2021, 56, 2029 doi: 10.1109/JSSC.2020.3040973
[19]
Yoo S W, Hung S C, Walling J S, et al. A 0.26mm2 DPD-less quadrature digital transmitter with <–40dB EVM over >30dB Pout range in 65nm CMOS. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2020, 184 doi: 10.1109/ISSCC19947.2020.9063070
[20]
Babamir S M, Razavi B. A digital RF transmitter with background nonlinearity correction. IEEE J Solid State Circuits, 2020, 55, 1502 doi: 10.1109/JSSC.2020.2968796
[21]
Lemberg J, Martelius M, Roverato E, et al. A 1.5–1.9-GHz all-digital tri-phasing transmitter with an integrated multilevel class-D power amplifier achieving 100-MHz RF bandwidth. IEEE J Solid State Circuits, 2019, 54, 1517 doi: 10.1109/JSSC.2019.2902753
[22]
Yin Y, Xiong L, Zhu Y T, et al. A compact dual-band digital polar Doherty power amplifier using parallel-combining transformer. IEEE J Solid State Circuits, 2019, 54, 1575 doi: 10.1109/JSSC.2019.2896407
[23]
Khamaisi B, Ben-Haim D, Nazimov A, et al. A 16nm, 28dBm dual-band all-digital polar transmitter based on 4-core digital PA for wi-Fi6E applications. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 2022, 324 doi: 10.1109/ISSCC42614.2022.9731624
[24]
Nguyen H M, Walling J S, Zhu A D, et al. A mm-wave switched-capacitor RFDAC. IEEE J Solid State Circuits, 2022, 57, 1224 doi: 10.1109/JSSC.2022.3142718
[25]
Qian H J, Shu Y Y, Zhou J, et al. A 20–32-GHz quadrature digital transmitter using synthesized impedance variation compensation. IEEE J Solid State Circuits, 2020, 55, 1297 doi: 10.1109/JSSC.2020.2964411
[26]
Yang B, Z. Deng Z, Qian H J, et al. 71-89GHz 12Gb/s double-edge-triggered quadrature power-DAC with LO leakage suppression achieving 20.5dBm peak output power and 20.4% system efficiency. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 286
[27]
Sireesh S K, Abkenar S H, Christoffers N, et al. A 4b RFDAC at 8GS/s for FMCW chirps with 4GHz bandwidth in 10 μs. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 376
[28]
Guo Y, Li Y, Huang W, et al. A polar-modulation-based cryogenic qubit state controller in 28nm bulk CMOS. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 508

Table 1.   Performance metrics of DTX/DPAs at sub-6 GHz and mm-wave bands (2019–2023).

Performance metricSystem effectArchitecture/design technique
Multi-mode
Multi-band		Flexibility and low costQuadrature/polar dual-mode reconfigurable[2]; wideband DTC/DPC-based phase modulation[3, 4]; sliding digital-IF quadrature DTX[5]
Output powerCommunication rangePower combining with stacked device[6, 7]; multiphase beamforming[8]; IQ cell-sharing[9]
Power efficiencyBattery lifeTime-interleaving Doherty class-G[10]; switched transformer[11]; multi-subharmonic switching[12]; class-G[13, 14]; Doherty[15]; complex-domain Doherty [9]; hybrid Doherty and impedance boosting[16, 17]; class-G Doherty[18]
LinearityData error rate and modulation typePhase nonlinearity compensation[15]; switch impedance linearization and code mapping[19]; ADC background correction[20]; tri-phasing modulation[21]
Signal bandwidthData rate and license costDual-band matching[22, 23]; edge combining class-D[24]; mm-wave power-DAC [25]; doubled-edge- triggered RFDAC[26]
DownLoad: CSV
[1]
Chan C H, Cheng L, Deng W, et al. Trending IC design directions in 2022. J Semicond, 2022, 43, 071401 doi: 10.1088/1674-4926/43/7/071401
[2]
Yin Y, Zhu Y T, Xiong L, et al. A compact transformer-combined polar/quadrature reconfigurable digital power amplifier in 28-nm logic LP CMOS. IEEE J Solid State Circuits, 2019, 54, 709 doi: 10.1109/JSSC.2018.2878831
[3]
Hu C X, Yin Y, Li T, et al. A fully-integrated wideband digital polar transmitter with 11-bit digital-to-phase converter in 40nm CMOS. IEEE J Solid State Circuits, 2023, 58, 462 doi: 10.1109/JSSC.2022.3192281
[4]
Palaskas Y, Madoglio P, Angel J, et al. A cellular multiband DTC-based digital polar transmitter with −153-dBc/Hz noise in 14-nm FinFET. IEEE J Solid-State Circuits, 2020, 55, 1830 doi: 10.1109/JSSC.2020.2987698
[5]
Hu C, Zheng D, Yin Y, et al. A 0.7-2.5GHz sliding digital-IF quadrature digital transmitter achieving >40% system efficiency for multi-mode NB-IoT/BLE applications. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 472
[6]
Yang B Z, Qian H J, Wang T Y, et al. A CMOS wideband watt-level 4096-QAM digital power amplifier using reconfigurable power-combining transformer. IEEE J Solid State Circuits, 2022, 58, 357 doi: 10.1109/JSSC.2022.3191975
[7]
Li J, Yin Y, Chen H, et al. A 4.1W quadrature doherty digital power amplifier with 33.6% peak pae in 28nm bulk CMOS. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 370
[8]
Bai Z D, Yuan W, Azam A, et al. 4.3 A multiphase interpolating digital power amplifier for TX beamforming in 65nm CMOS. 2019 IEEE International Solid-State Circuits Conference (ISSCC), 2019, 78 doi: 10.1109/ISSCC.2019.8662430
[9]
Zheng D Y, Yin Y, Zhu Y T, et al. 24.5 A 15b quadrature digital power amplifier with transformer-based complex-domain power-efficiency enhancement. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020, 370 doi: 10.1109/ISSCC19947.2020.9062959
[10]
Yoo S W, Hung S C, Yoo S M. 24.4 A watt-level multimode multi-efficiency-peak digital polar power amplifier with linear single-supply class-G technique. 2020 IEEE International Solid-State Circuits Conference (ISSCC), 2020, 368 doi: 10.1109/ISSCC19947.2020.9063069
[11]
Xiong L, Li T, Yin Y, et al. A broadband switched-transformer digital power amplifier for deep back-off efficiency enhancement. 2019 IEEE International Solid-State Circuits Conference (ISSCC), 2019, 76 doi: 10.1109/JSSC.2020.3005798
[12]
Zhang A Y, Chen M S W. A subharmonic switching digital power amplifier for power back-off efficiency enhancement. IEEE J Solid State Circuits, 2019, 54, 1017 doi: 10.1109/JSSC.2019.2893534
[13]
Yoo S W, Hung S C, Yoo S M. A watt-level quadrature class-G switched-capacitor power amplifier with linearization techniques. IEEE J Solid State Circuits, 2019, 54, 1274 doi: 10.1109/JSSC.2019.2904209
[14]
Bechthum E, El Soussi M, Dijkhuis J F, et al. A CMOS polar class-G switched-capacitor PA with a single high-current supply, for LTE NB-IoT and eMTC. IEEE J Solid State Circuits, 2019, 54, 1941 doi: 10.1109/JSSC.2019.2910407
[15]
Jung D, Li S S, Park J S, et al. A CMOS 1.2-V hybrid current- and voltage-mode three-way digital Doherty PA with built-In phase nonlinearity compensation. IEEE J Solid State Circuits, 2020, 55, 525 doi: 10.1109/JSSC.2019.2953832
[16]
Qian H J, Yang B Z, Zhou J, et al. A quadrature digital power amplifier with hybrid Doherty and impedance boosting for complex domain power back-off efficiency enhancement. IEEE J Solid State Circuits, 2021, 56, 1487 doi: 10.1109/JSSC.2021.3059113
[17]
Yang B Z, Qian H J, Luo X. Quadrature switched/floated capacitor power amplifier with reconfigurable self-coupling canceling transformer for deep back-off efficiency enhancement. IEEE J Solid State Circuits, 2021, 56, 3715 doi: 10.1109/JSSC.2021.3113511
[18]
Hung S C, Yoo S W, Yoo S M. A quadrature class-G complex-domain Doherty digital power amplifier. IEEE J Solid State Circuits, 2021, 56, 2029 doi: 10.1109/JSSC.2020.3040973
[19]
Yoo S W, Hung S C, Walling J S, et al. A 0.26mm2 DPD-less quadrature digital transmitter with <–40dB EVM over >30dB Pout range in 65nm CMOS. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2020, 184 doi: 10.1109/ISSCC19947.2020.9063070
[20]
Babamir S M, Razavi B. A digital RF transmitter with background nonlinearity correction. IEEE J Solid State Circuits, 2020, 55, 1502 doi: 10.1109/JSSC.2020.2968796
[21]
Lemberg J, Martelius M, Roverato E, et al. A 1.5–1.9-GHz all-digital tri-phasing transmitter with an integrated multilevel class-D power amplifier achieving 100-MHz RF bandwidth. IEEE J Solid State Circuits, 2019, 54, 1517 doi: 10.1109/JSSC.2019.2902753
[22]
Yin Y, Xiong L, Zhu Y T, et al. A compact dual-band digital polar Doherty power amplifier using parallel-combining transformer. IEEE J Solid State Circuits, 2019, 54, 1575 doi: 10.1109/JSSC.2019.2896407
[23]
Khamaisi B, Ben-Haim D, Nazimov A, et al. A 16nm, 28dBm dual-band all-digital polar transmitter based on 4-core digital PA for wi-Fi6E applications. 2022 IEEE International Solid-State Circuits Conference (ISSCC), 2022, 324 doi: 10.1109/ISSCC42614.2022.9731624
[24]
Nguyen H M, Walling J S, Zhu A D, et al. A mm-wave switched-capacitor RFDAC. IEEE J Solid State Circuits, 2022, 57, 1224 doi: 10.1109/JSSC.2022.3142718
[25]
Qian H J, Shu Y Y, Zhou J, et al. A 20–32-GHz quadrature digital transmitter using synthesized impedance variation compensation. IEEE J Solid State Circuits, 2020, 55, 1297 doi: 10.1109/JSSC.2020.2964411
[26]
Yang B, Z. Deng Z, Qian H J, et al. 71-89GHz 12Gb/s double-edge-triggered quadrature power-DAC with LO leakage suppression achieving 20.5dBm peak output power and 20.4% system efficiency. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 286
[27]
Sireesh S K, Abkenar S H, Christoffers N, et al. A 4b RFDAC at 8GS/s for FMCW chirps with 4GHz bandwidth in 10 μs. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 376
[28]
Guo Y, Li Y, Huang W, et al. A polar-modulation-based cryogenic qubit state controller in 28nm bulk CMOS. Proc IEEE Int Solid-State Circuits Conf (ISSCC), 2023, 508
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1. Cao, L., Yin, Y. Analysis of Polar and Quadrature Digital Transmitters for Wi-Fi7 Applications. 2024. doi:10.1109/ICSICT62049.2024.10831745

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    Yun Yin, Hongtao Xu. Digital-intensive RFIC design techniques for transmitters in ISSCC 2023[J]. Journal of Semiconductors, 2023, 44(4): 040203. doi: 10.1088/1674-4926/44/4/040203
    Y Yin, H T Xu. Digital-intensive RFIC design techniques for transmitters in ISSCC 2023[J]. J. Semicond, 2023, 44(4): 040203. doi: 10.1088/1674-4926/44/4/040203
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    Received: 13 March 2023 Revised: Online: Accepted Manuscript: 17 March 2023Uncorrected proof: 17 March 2023Published: 10 April 2023

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      Yun Yin, Hongtao Xu. Digital-intensive RFIC design techniques for transmitters in ISSCC 2023[J]. Journal of Semiconductors, 2023, 44(4): 040203. doi: 10.1088/1674-4926/44/4/040203 ****
      Y Yin, H T Xu. Digital-intensive RFIC design techniques for transmitters in ISSCC 2023[J]. J. Semicond, 2023, 44(4): 040203. doi: 10.1088/1674-4926/44/4/040203
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      Digital-intensive RFIC design techniques for transmitters in ISSCC 2023

      DOI: 10.1088/1674-4926/44/4/040203

      • State Key Laboratory of Integrated Chips and Systems, Department of Microelectronics, Fudan University, Shanghai 201203, China

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      • Yun Yin：received the B.S. degree in microelectromechanical systems and the Ph.D. degree in microelectronics from Tsinghua University, Beijing, China, in 2010 and 2015, respectively. She joined the School of Microelectronics, Fudan University, Shanghai, China, where she is currently an Associate Professor. Her research interest focuses on analog/RF integrated circuit design, including multimode multiband software defined radio (SDR) transceiver, CMOS analog power amplifier (PA) and all-digital transmitter for cellular, Wi-Fi, and low-power internet of things (IoT) applications
      • Hongtao Xu：received the B.S. degree in electronic engineering from Fudan University, Shanghai, China, in 1997, and the M.A. degree in economics and the Ph.D. degree in electrical and computer engineering from the University of California at Santa Barbara, Santa Barbara, CA, USA, in 2003 and 2005, respectively. In 2015, he joined the School of Microelectronics, Fudan University, as a Full Professor. He has authored or coauthored more than 70 journal articles and conference papers. He holds 16 patents in the areas of RF transceiver and front-end module. His technical interests include innovative analog/RF/millimeter-wave circuits and wireless system for communication and sensing
      • Corresponding author: yiny@fudan.edu.cn; hongtao@fudan.edu.cn
      • Received Date: 2023-03-13
        Available Online: 2023-03-17

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