| Citation: |
Zhao Zhang. CMOS phase-locked loops in ISSCC 2023[J]. Journal of Semiconductors, 2023, 44(5): 050205. doi: 10.1088/1674-4926/44/5/050205
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Z Zhang. CMOS phase-locked loops in ISSCC 2023[J]. J. Semicond, 2023, 44(5): 050205. doi: 10.1088/1674-4926/44/5/050205
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CMOS phase-locked loops in ISSCC 2023
DOI: 10.1088/1674-4926/44/5/050205
More Information
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Zhao Zhang：received the B.S. degree from Beijing University of Posts and Telecommunications, Beijing, China, in 2011, and the Ph.D. degree from Institute of Semiconductors, Chinese Academy of Sciences (IOSCAS), Beijing, China, in 2016. Since 2020, he joined in the IOSCAS, Beijing, where he is currently a Full Professor. He has gained National Science Fund for Excellent Young Scholars from NSFC in 2022, and he is the associated editor of IET Electronics Letters. His research interests include the design of wireline transceivers, low-jitter and low-power PLLs, and ultra-low voltage ICs for bio/energy-harvesting applications - Corresponding author: zhangzhao11@semi.ac.cn
- Accepted Date: 2023-04-26 Available Online: 2023-04-26
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References
[1] Renukaswamy P T, Vaesen K, Markulic N, et al. A 16GHz, 41kHzrms frequency error, background-calibrated, duty-cycled FMCW charge-pump PLL. IEEE International Solid-State Circuit Conference, 2023, 68 doi: 10.1109/ISSCC42615.2023.10067404[2] Jo Y, Kim J, Shin Y, et al. A 135fsrms-jitter 0.6-to-7.7GHz LO generator using a single LC-VCO-based subsampling PLL and a ring-oscillator-based sub-integer-N frequency multiplier. IEEE International Solid-State Circuit Conference, 2023, 71 doi: 10.1109/ISSCC42615.2023.10067748[3] Dartizio1 S M, Tesolin F, Castoro1 G, et al. A 76.7fs-integrated-jitter and -71.9dBc in-band fractional-spur bang-bang digital PLL based on an inverse-constant-slope DTC and FCW subtractive dithering. IEEE International Solid-State Circuit Conference, 2023, 74 doi: 10.1109/ISSCC42615.2023.10067719[4] Qiu J, Wang W, Sun Z, et al. A 32kHz-reference 2.4GHz fractional-N nonuniform oversampling PLL with gain-boosted PD and loop-gain calibration. IEEE International Solid-State Circuit Conference, 2023, 77 doi: 10.1109/ISSCC42615.2023.10067516[5] Castoro G, Dartizio S M, Tesolin F, et al. A 9.25GHz digital PLL with fractional-spur cancellation based on a multi-DTC topology. IEEE International Solid-State Circuit Conference, 2023, 80 doi: 10.1109/ISSCC42615.2023.10067351[6] Bang J, Kim J, Jung S, et al. A 47fsrms-jitter and 26.6mW 103.5GHz PLL with power-gating injection-locked frequency-multiplier-based phase detector and extended loop bandwidth. IEEE International Solid-State Circuit Conference, 2023, 83 doi: 10.1109/ISSCC42615.2023.10067293[7] Zhang Z, Shen X, Zhang Z, et al. A 0.4V-VDD 2.25-to-2.75GHz ULV-SS-PLL achieving 236.6fsrms jitter, -253.8dB jitter-power FoM, and -76.1dBc reference spur. IEEE International Solid-State Circuit Conference, 2023, 86 doi: 10.1109/ISSCC42615.2023.10067638 -
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