Abstract: We design a reconfigurable pipelined multiplier embedded in an FPGA.This design is based on the modified Booth algorithm and performs 18×18 signed or 17×17 unsigned multiplication.We propose a novel method for circuit optimization to reduce the number of partial products.A new layout floorplan design of the multiplier block is reported to comply with the constraints imposed by the tile-based FPGA chip design.The multiplier can be configured as synchronous or asynchronous.Its operation can also be configured as pipelined for high-frequency operation.This design can be easily extended for different input and output bit-widths.We employ a novel carry look-ahead adder circuit to generate the final product.The transmission-gate logic is used for the low-level circuits throughout the entire multiplier for fast logic operations.The design of the multiplier block is based on SMIC 0.13μm CMOS technology using full-custom design methodology.The operation of the 18×18 multiplier takes 4.1ns.The two-stage pipelined operation cycle is 2.5ns.This is 29.1% faster than the commercial multiplier and is 17.5% faster than the multipliers reported in other academic designs.Compared with the distributed LUT-based multiplier,it demonstrates an area efficiency ratio of 33∶1.

Key words: FPGA, multiplier, reconfigurable, modified Booth algorithm, CLA, transmission-gate logic