Abstract: This paper presents a new quasi-static single-phase energy recovery logic (QSSERL), which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control voltages.This not only ensures lower energy dissipation,but also simplifies the clock design,which would be otherwise more complicated due to the signal synchronization requirement.It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts.Simulation with an 8bit logarithmic look-ahead adder (LLA) using static CMOS,clocked CMOS adiabatic logic (CAL,an existing typical single-phase energy recovery logic),and QSSERL,under 128 randomly generated input vectors,shows that the power consumption of the QSSERL adder is only 45% of that of the conventional static CMOS counterpart at 10MHz, and the QSSERL adder achieves better energy efficiency than CAL when the input frequency f input is larger than 2MHz.

Key words: energy recovery, adiabatic logic, low power, digital CMOS, VLSI