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| Citation: |
Liu Yongwang, Wang Zhigong, Li Wei. 1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop[J]. Journal of Semiconductors, 2006, 27(12): 2190-2195.
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Liu Y W, Wang Z G, Li W. 1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop[J]. Chin. J. Semicond., 2006, 27(12): 2190.
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1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop
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Abstract
A low-power phase-locked loop (PLL) is designed and fabricated in TSMC’s standard 0.25μm CMOS process.A behavioral simulation method for the PLL’s phase noise is presented.The power consumption of the PLL core is about 12mW.The rms jitter is 6.1ps,and the SSB phase noise is -106dBc/Hz at a 10kHz offset.-
Keywords:
- PLL,
- PFD,
- charge pump,
- VCO
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References
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Proportional views
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