| Citation: |
Chen Yongcong. Design Technique to Restrain Reference Spursin CMOS Phase Lock Loops[J]. Journal of Semiconductors, 2006, 27(12): 2196-2202.
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Chen Y C. Design Technique to Restrain Reference Spursin CMOS Phase Lock Loops[J]. Chin. J. Semicond., 2006, 27(12): 2196.
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Design Technique to Restrain Reference Spursin CMOS Phase Lock Loops
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Abstract
We first analyze the source of reference spurs.Then we present some design techniques to restrain them.These techniques include improving the matching between the up current and down current in the charge pump,alleviating the charge injection and clock feed-through of the charge pump’s switch,matching the up/down branch of the PFD,and enhancing the isolation of the PLL both in IC and PCB.Two PLLs designed for PCI-express transceivers are fabricated in a TSMC 0.13μm CMOS process. Measurement results show that these methods are effective-
Keywords:
- PLL,
- reference-spur,
- frequency-synthesizer,
- CDR,
- phase-noise,
- jitter
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References
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Proportional views
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