Abstract: This paper presents the design considerations and implementation of an area-efficient interpolator suitable for a delta-sigma D/A converter.In an effort to reduce the area and design complexity,a method for designing an FIR filter as a tapped cascaded interconnection of identical subfilters is modified.The proposed subfilter structure further minimizes the arithmetic number.Experimental results show that the proposed interpolator achieves the design specification,exhibiting high performance and hardware efficiency,and also has good noise rejection capability.The interpolation filter can be applied to a delta-sigma DAC and is fully functional.

Key words: delta-sigma digital-to-analog converter, interpolator, halfband filter