PAPERS
Abstract: A monolithic 2.5Gbps/ch 2-channel parallel clock and data recovery circuit is designed and fabricated in TSMC’s standard 0.18μm CMOS process.PLL and DLL techniques are applied to implement the IC.Compared with conventional circuits,the recovered parallel data is bit-synchronous,and the reference clock is avoided.The rms jitter of the recovered clock is 2.6ps for 2 parallel PRBS input data (231-1).The rms jitters of the two recovered data are 3.3 and 3.4ps,respectively.
Key words: parallel clock and data recovery, DLL, PLL, bit-synchronous
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Received: 18 August 2015 Revised: 06 October 2006 Online: Published: 01 March 2007
| Citation: |
Liu Yongwang, Wang Zhigong, Li Wei. 2.5Gbps/ch 2-Channel Parallel Clock and Data Recovery Circuit[J]. Journal of Semiconductors, 2007, 28(3): 460-464.
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Liu Y W, Wang Z G, Li W. 2.5Gbps/ch 2-Channel Parallel Clock and Data Recovery Circuit[J]. Chin. J. Semicond., 2007, 28(3): 460.
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