Chin. J. Semicond. > 2004, Volume 25 > Issue 5 > 508-515
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CEE-Gr:一个在多约束下进行性能优化的总体布线器(英文)

张凌 , 经彤 , 洪先龙 and 许静宇

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Key words: VLSI/ULSI, 布图设计, 总体布线, 多约束, 性能优化

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    Received: 19 August 2015 Revised: Online: Published: 01 May 2004

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      Article Navigation >  Journal of Semiconductors  > 2004  >  25(5): 508-515
      张凌, 经彤, 洪先龙, 许静宇. CEE-Gr:一个在多约束下进行性能优化的总体布线器(英文)[J]. 半导体学报(英文版), 2004, 25(5): 508-515.
      Citation:
      张凌, 经彤, 洪先龙, 许静宇. CEE-Gr:一个在多约束下进行性能优化的总体布线器(英文)[J]. 半导体学报(英文版), 2004, 25(5): 508-515.
      shu

      • Received Date: 2015-08-19

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