PAPERS
Ye Fan, Shi Yufeng, Guo Yao, Luo Lei, Xu Jun and Ren Junyan
Abstract: This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter (ADC) based on an improved 1.5bit/stage architecture.The ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 57dB and maintains 51dB up to 57MHz,the Nyquist frequency for a clock rate of 100Msample/s.The differential non-linearity (DNL) and integral non-linearity (INL) are typically measured as 0.3LSB and 1.0LSB,respectively.The ADC is implemented in a 0.18μm mixed-signal CMOS technology and occupies 0.76mm2.
Key words: analog-to-digital converter, pipeline, improved 1.5bit/stage architecture
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A 13-bit, 8 MSample/s pipeline A/D converter Guo Dandan, Li Fule, Zhang Chun, Wang Zhihua Journal of Semiconductors, 2009, 30(2): 025006. doi: 10.1088/1674-4926/30/2/025006 |
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A novel low-voltage operational amplifier for low-power pipelined ADCs Fan Mingjun, Ren Junyan, Guo Yao, Li Ning, Ye Fan, et al. Journal of Semiconductors, 2009, 30(1): 015009. doi: 10.1088/1674-4926/30/1/015009 |
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| 17 |
Wei Qi, Yin Xiumei, Yang Bin, Yang Huazhong Journal of Semiconductors, 2008, 29(5): 1010-1015. |
| 18 |
A 1.8V 10bit 100Msps Pipelined Analog to Digital Converter Long Shanli, Shi Longxing, Wu Jianhui, Wang Pei Journal of Semiconductors, 2008, 29(5): 923-929. |
| 19 |
A Novel Sampling Switch Suitable for Low-Voltage Analog-to-Digital Converters Peng Yunfeng, Zhou Feng Chinese Journal of Semiconductors , 2006, 27(8): 1367-1372. |
| 20 |
A 10bit, 50Msample/s,57.6mW CMOS Pipeline A/D Converter Huang Feipeng, Wang Jingguang, He Jirou, Hong Zhiliang Chinese Journal of Semiconductors , 2005, 26(11): 2230-2235. |
Article views: 3656 Times PDF downloads: 1555 Times Cited by: 0 Times
Received: 18 August 2015 Revised: 14 August 2008 Online: Published: 01 December 2008
| Citation: |
Ye Fan, Shi Yufeng, Guo Yao, Luo Lei, Xu Jun, Ren Junyan. A 10bit 100MS/s Pipelined ADC with an Improved 1.5bit/Stage Architecture[J]. Journal of Semiconductors, 2008, 29(12): 2359-2363.
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Ye F, Shi Y F, Guo Y, Luo L, Xu J, Ren J Y. A 10bit 100MS/s Pipelined ADC with an Improved 1.5bit/Stage Architecture[J]. J. Semicond., 2008, 29(12): 2359.
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