| Citation: |
Ye Fan, Shi Yufeng, Guo Yao, Luo Lei, Xu Jun, Ren Junyan. A 10bit 100MS/s Pipelined ADC with an Improved 1.5bit/Stage Architecture[J]. Journal of Semiconductors, 2008, 29(12): 2359-2363.
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Ye F, Shi Y F, Guo Y, Luo L, Xu J, Ren J Y. A 10bit 100MS/s Pipelined ADC with an Improved 1.5bit/Stage Architecture[J]. J. Semicond., 2008, 29(12): 2359.
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A 10bit 100MS/s Pipelined ADC with an Improved 1.5bit/Stage Architecture
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Abstract
This paper presents a 10bit 100MS/s CMOS pipelined analog-to-digital converter (ADC) based on an improved 1.5bit/stage architecture.The ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 57dB and maintains 51dB up to 57MHz,the Nyquist frequency for a clock rate of 100Msample/s.The differential non-linearity (DNL) and integral non-linearity (INL) are typically measured as 0.3LSB and 1.0LSB,respectively.The ADC is implemented in a 0.18μm mixed-signal CMOS technology and occupies 0.76mm2. -
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