Abstract: A novel MBE-grown method using low-temperature (LT) Si technology is introduced into the fabrication of strained Si channel heterojunction pMOSFETs.By sandwiching a low-temperature Si layer between Si buffer and SiGe layer,the strain relaxation degree of the SiGe layer is increased.At the same time,the threading dislocations (TDs) are hold back from propagating to the surface and result a TD density less than 1E6cm-2.The LT-Si technology also reduces thickness of relaxed Si1-xGex epitaxy layer from several μm using UHVCVD to less than 400nm (x=0.2),which will improve the heat dissipation of devices.AFM tests of strained Si surface show RMS is less than 1.02nm.The I-V measurements indicate that hole mobility has an enhancement of 25% compared to similarly processed bulk Si pMOSFET.

Key words: strained Si,  SiGe,  heterojunction field effect transistor,  molecular beam, 弛豫